RT3052F datasheet(73/235 Pages) ETC1

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RT3050/52

Datasheet

Preliminary

Revision August 14, 2008

DSR3050/52_V.2.0_081408

-73-

Form No.：QS-073-F02

Rev.：1

Kept by： DCC

Ret. T ime： 5 Years

GDMACT1n: GDMA Channel n Control Register 1 (offset: 0x0C, 0x1C, 0x2C, 0x3C, 0x4C, 0x5C, 0x6C, 0x7C)

Bits

Type

Name

Description

Initial value

31:5

Reserved

R/W

Channel

Unmasked

Interrupt

Enable

Channel unmasked interrupt enabl e.

‘b1:Enable

‘b0:Disable

When this bit is set, an interrupt will be asserted when the

hardware wants to clear the Channel Mask bit and the Channel

Mask bit is 0 originally.

1’b0

3:1

R/W

Next Unmasked

Channel

The value represents the next unmasked channel . When the

transaction is done, the hardware will clear the Channel Mask bit

of the next unmasked channel.

‘b000: Channel 0

‘b001: Channel 1

‘b010: Channel 2

‘b011: Channel 3

‘b100: Channel 4

‘b101: Channel 5

‘b110: Channel 6

‘b111: Channel 7

If the hardware doesn’t need to clear any Channel Mask bit,

these bits must be set to their own channel.

4’b0

R/W

Channel Mask

‘b1: This channel is masked

‘b0: This channel is not masked

When this channel mask is set, the GDMA transaction will not

start until this bit is clear by the hardware.

1’b0

GDMAISTS: GDMA Interrupt Status Register (offset: 0x80)

Bits

Type

Name

Description

Initial value

31:24 -

Reserved

23:16 R/W1C

Unmasked

Interrupt Status

This register contains the unmasked interrupt status. This bit will

be set when the hardware wants to clear the Channel Mask bit

and the Channel Mask bit is 0 originally.

Bit23~bit16 is for channel 7 ~ channel 0, respectively.

8’b0

15:8

Reserved

7:0

R/W1C

Transmit Done

Interrupt Status

This register contains the transmit-done interrupt status.

Bit7~bit0 is for channel 7 ~ channel 0, respectively.

8’b0

GDMASSTS: GDMA Signal Status Register (offset: 0x84)

Bits

Type

Name

Description

Initial value

31:24 -

Reserved

23:16 R

GDMA Request

Signal Status

This register contains the GDMA Request Signals status

Bit7~bit0 is for GDMA_REQ7 ~ GDMA_REQ0, r espectively.

8’b0

15:8

GDMA ACK

Signal Status

This register contains the GDMA ACK signals status

Bit7~bit0 is for GDMA_ACK7 ~ GDMA_ACK0, r espectively.

8’b0

7:0

GDMA Finish

Signal Status

This register contains the GDMA Finish signals status

Bit7~bit0 is for GDMA_Finish7 ~ GDMA_Finish0, respectively.

8’b0

GDMAGCT: GDMA Global Control Register (offset: 0x88)

Bits

Type

Name

Description

Initial value

31:1

Reserved

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