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4. Peripheral Interface

4.2. General Purpose Input Output (GPIO)

ESP8089 16 GPIO pins. They can be assigned to various functions by the firmware. Each

GPIO can be configured with internal pull-up/down, input available for sampling by a

software register, input triggering an edge or level CPU interrupt, input triggering a level

wakeup interrupt, open-drain or push-pull output driver, or output source from a software

register, or a sigma-delta PWM DAC.

These pins are multiplexed with other functions such as host interface, UART, SI, Bluetooth

co-existence, etc.

4.3. Real Time Clock IO (EXT_LFC)

If a 32.768 kHz LFC clock is available, it can be connected to EXT_LFC. If no clock is

available on this pin, the internal LFC will be used. If an EXT_LFC is available, the selection

of LFC source, internal LFC or EXT_LFC can be done by a strapping pin.

4.4. Digital IO Pads

The digital IO pads are bidirectional, non-inverting and tri-state. It includes input and an

output buffer with tri-state control inputs. Besides this, for low power operations, the IO can

also be set to hold. For instance, when we power down the chip, all output enable signals

can be set to hold low.

An optional hold functionality can be built into the IO if requested. When the IO is not driven

by the internal or external circuitry, the hold functionality can be used to hold the state to

the last used state.

The hold functionality introduces some positive feedback into the pad. Hence, the external

driver that drives the pad must be stronger than the positive feedback. The required drive

strength, however, is small – in the range of 5 μA.

All digital IO pins are protected from over-voltage with a snap-back circuit connected

between the pad and the ground. The snap back voltage is typically about 6V, and the

holding voltage is 5.8V. This provides protection from over-voltages and ESD. The output

devices are also protected from reversed voltages with diodes.

Espressif

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