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CDCE6214RGET Datasheet(PDF) 30 Page - Texas Instruments

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Part # CDCE6214RGET
Description  CDCE6214 Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM
PDF  53 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE6214RGET Datasheet(HTML) 30 Page - Texas Instruments

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CDCE6214
SNAS811 – JULY 2020
www.ti.com
Product Folder Links: CDCE6214
Submit Documentation Feedback
Copyright © 2020, Texas Instruments Incorporated
Table 17. GPIO Input/Output Signal List
ABBREVIATION
TYPE
DESCRIPTION
FREQ_INC
Input
Frequency Increment; Increments the MASH
numerator
FREQ_DEC
Input
Frequency Decrement; Decrements the
MASH numerator
OE (global)
Input
Enables or disables all differential outputs
Y[4:1] (bypass not affected)
SSC_EN
Input
Enables or disables SSC.
OE1
Input
Enables or disables OUT1
OE2
Input
Enables or disables OUT2
OE3
Input
Enables or disables OUT3
OE4
Input
Enables or disables OUT4
PLL_LOCK
Output
PLL Lock Status. 0 = PLL out of lock; 1 =
indicates PLL in lock
9.4 Device Functional Modes
9.4.1 Operation Modes
The operating modes listed in Table 18 can be set, and the GPIOs configured. An operating mode change only
becomes effective when it is loaded from the EEPROM after a power cycle.
Table 18. Modes of Operations
DESCRIPTION
MODE
REFSEL
HW_SW_CTRL
GPIO1
GPIO2
GPIO3
GPIO4
I2C + GPIO
Fall-back
M
M
I/O
SDA
SCL
I/O
OE
Pin Mode
L/H
L/H
OE1
OE2
OE3
OE4
I2C + GPIO
Serial Interface
Mode
L/H
L/H
I/O
SDA
SCL
I/O
9.4.1.1 Fall-Back Mode
As the programming interface can be intentionally deactivated using the EEPROM, an accidental disabling of the
I2C blocks further access to the device. The serial interface can be forced using the fall-back mode. To enter this
mode, the user leaves pin 4 and pin 23 floating while the supply voltage is applied to VDDREF. In this mode,
EEPROM Read at power up is bypassed and device boots in default mode. In this mode, pin 11 is pre-
configured as an input and pin 20 is configured as an output. After powering up in fall-back mode, the device can
be re-programmed through serial interface and be re-configured for normal operation. EEPROM can also be re-
programmed. The PLL would not be auto-calibrated, however, and the I2C interface would be active. This mode
would allow the user to fully configure the device before re-locking the PLL.
9.4.1.2 Pin Mode
In pin mode, the pins 12 and 19 are input pins which act as individual output enable pins. Together with pins 11
and 20, this allows for one output enable pin per output channel.
9.4.1.3 Serial Interface Mode
In serial interface mode, pins 12 and 19 are configured as an I2C interface.
9.5 Programming
9.5.1 I2C Serial Interface
The CDCE6214 ultra-low power clock generator provides an I2C-compatible serial interface for register and
EEPROM access. The device is compatible to standard-mode I2C at 100 kHz and the fast-mode I2C at 400-kHz
clock frequency.
1. In fall-back mode, I2C slave address = 67h.



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