TLE9461ES datasheet(113/140 Pages) INFINEON

113 / 140 page

TLE9461ES

Lite CAN SBC Family

Serial Peripheral Interface

Datasheet

113

Rev.1.1

2019-09-27

Notes

1. See also Chapter 12.5 for selection of VCC1 undervoltage hysteresis

2. See also Chapter 12.8 for minimum waiting time in case of an TSD2 event

3. The bit CFG_LOCK_0 is used to prevent an unintentional modification of the charge pump activation bit

CP_EN and the GPIO configuration bits GPIO. In case the charge pump output state or the GPIO configuration

must be changed then it is necessary to clear CFG_LOCK_0. The other lockable bits are controlled by the lock

bit CFG_LOCK_1. In case either lock bit is set then the respective locked bits cannot be changed by a soft reset.

Therefore, the respective soft reset values are marked as ‘y’.

4. In case CFG_LOCK_1 bit are set, then the respective soft reset value is like the Restart value.

HW_CTRL_1

Hardware Control 1 (Address 000 1110B)

POR / Soft Reset Value: y0yy y000B;

Restart Value: x0xx x000B

RSTN_HYS

Reserved

TSD2_DEL

RSTN_DEL CFG_LOCK_0

Reserved

rwl

Field

Bits

Type

Description

RSTN_HYS

7rwl

VCC1 Undervoltage Reset Hysteresis Selection (see also

Chapter 12.5.1 for more information)

, default hysteresis applies as specified in the electrical

characteristics table

, the highest rising threshold (Vrt1,r) is always used for the

release of the undervoltage reset

Reserved

Reserved, always reads as 0

TSD2_DEL

5rwl

TSD2 Minimum Waiting Time Selection

, Minimum waiting time until TSD2 is released again is always

, Minimum waiting time until TSD2 is released again is 1s,

after >16 consecutive TSD2 events, it is extended to x64

RSTN_DEL

4rwl

Reset Delay Time Selection

, The extended reset delay time tRD1is selected (default)

, The reduced tRD2 reset delay time is selected

CFG_LOCK_0 3rw

Configuration Lock Bit - Level 0

, CP_EN and GPIO can be modified

, CP_EN and GPIO is locked and cannot be modified

Reserved

2:0

Reserved, always reads as 0

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