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TLE9461ES Datasheet(PDF) 118 Page - Infineon Technologies AG |
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TLE9461ES Datasheet(HTML) 118 Page - Infineon Technologies AG |
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118 / 140 page  TLE9461ES Lite CAN SBC Family Serial Peripheral Interface Datasheet 118 Rev.1.1 2019-09-27 13.6 SPI Status Information Registers READ/CLEAR Operation (see also Chapter 13.3): • One 16-bit SPI command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to the SPI bits 8...15 (see also figure). • There are two different bit types: - ‘r’ = READ: read only bits (or reserved bits) - ‘rc’ = READ/CLEAR: readable and clearable bits • Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only) • Clearing a register is done byte wise by setting the SPI bit 7 to “1” • SPI status registers are in general not cleared or changed automatically (an exception are the WD_FAIL bits). This must be done by the microcontroller via SPI command The registers are addressed wordwise. Table 28 Register Overview: SPI Status Information Registers Register Short Name Register Long Name Offset Address Reset Value General Status Registers SUP_STAT_1 Supply Voltage Fail Status 100 0000B Page 119 SUP_STAT_0 Supply Voltage Fail Status 100 0001B Page 120 THERM_STAT Thermal Protection Status 100 0010B Page 121 DEV_STAT Device Information Status 100 0011B Page 121 BUS_STAT Bus Communication Status 100 0100B Page 122 WK_STAT_0 Wake-up Source and Information Status 0 100 0110B Page 123 WK_STAT_1 Wake-up Source and Information Status 1 100 0111B Page 123 WK_LVL_STAT WK Input Level 100 1000B Page 124 GPIO_OC_STAT GPIO Overcurrent Status 101 0100B Page 125 GPIO_OL_STAT GPIO Open-Load Status 101 0101B Page 125 Family and Product Information Register FAM_PROD_STAT Family and Product Identification Register 111 1110B Page 126 |
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