LM76005 datasheet(13/42 Pages) TI1

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EN _ VOUT _ H

ENT

ENB

IN _ ON _ H

EN_VOUT_H

VIN

ENABLE

RENT

RENB

LM76005-Q1

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SNVSBK6 – FEBRUARY 2020

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Feature Description (continued)

7.3.4 Enable (EN Pin) and UVLO

System UVLO by EN and VCC_UVLO voltage on the EN pin (VEN) controls the ON/OFF functionality of the

LM76005-Q1. Applying a voltage less than 0.3 V to the EN input shuts down the operation of the LM76005-Q1.

In shutdown mode, the quiescent current drops to typically 1.2 µA at VIN = 24 V.

The internal LDO output voltage VCC is turned on when VEN_VOUT_H is higher than 1.2 V. The LM76005-Q1

switching action and output regulation are enabled when VEN is greater than 1.204 V (typical). The LM76005-Q1

supplies regulated output voltage when enabled and output current up to 5 A. The EN pin is an input and cannot

be open circuit or floating. The simplest way to enable the operation of the LM76005-Q1 is to connect the EN pin

to PVIN pins directly. This allows self-start-up of the LM76005-Q1 when VIN is within the operation range.

Many applications can benefit from the employment of an enable divider RENT and RENB (see Figure 8) to

establish a precision system UVLO level for the stage. System UVLO can be used for supplies operating from

utility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply

protection, such as a battery. An external logic signal can also be used to drive EN input for system sequencing

and protection.

Figure 8. VIN UVLO

With a selected RENT, the RENB can be calculated by:

where

•

VIN_ON_H is the desired supply voltage threshold to turn on this device

•

VEN_VOUT_H can be taken from device data sheet

(4)

Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add

more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the

hundreds of k

Ω range is a good starting point.

7.3.5 Internal LDO, VCC UVLO, and Bias Input

The LM76005-Q1 has an internal LDO generating VCC voltage for control circuitry and MOSFET drivers. The

nominal voltage for VCC is 3.29 V. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed as close

as possible to the pin and properly grounded. Do not load or short the VCC pin to ground during operation.

Shorting the VCC pin to ground during operation can damage the device.

A UVLO prevents the LM76005-Q1 from operating until the VCC voltage exceeds VCC_UVLO. The VCC_UVLO

threshold is 3.14 V and has approximately 565 mV of hysteresis, so the device operates until VCC drops below

2.575 V (typical). Hysteresis prevents the device from turning off during power up if VIN droops due to input

current demands.

The LDO can generate VCC from two inputs: the supply voltage VIN and the BIAS input. The LDO power loss is

calculated by ILDO × (VINLDO – VOUTLDO). The higher the difference between the input and output voltages of the

LDO, the more losses occur to supply the same LDO output current. The BIAS input is designed to reduce the

difference of the input and output voltages of the LDO to improve efficiency, especially at light load. TI

recommends tying the BIAS pin to VOUT when the output voltage is equal to or greater than 3.3 V. Tie the BIAS

pin to ground for applications less than 3.3 V. BIAS can also tie to external voltage source if available to improve

efficiency. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor be used to bypass the

BIAS pin to ground. If there is high-frequency noise or voltage spikes present on VOUT (during transient events or

fault conditions), TI recommends connecting a resistor (1 to 10

Ω) between VOUT and BIAS.

LM76005 Datasheet(PDF) 13 Page - Texas Instruments

LM76005 Datasheet(HTML) 13 Page - Texas Instruments

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