RT1050 datasheet(4/110 Pages) NXP

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i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020

NXP Semiconductors

i.MX RT1050 introduction

– Support for SDXC (extended capacity)

— One 10/100 M Ethernet controller with support for IEEE1588

— Eight universal asynchronous receiver/transmitter (UARTs) modules

— Four I2C modules

— Four SPI modules

— Two FlexCAN modules

•

GPIO and Pin Multiplexing:

— General-purpose input/output (GPIO) modules with interrupt capability

— Input/output multiplexing controller (IOMUXC) to provide centralized pad control

— Two FlexIOs

The i.MX RT1050 processors integrate advanced power management unit and controllers:

•

Full PMIC integration. On-chip DCDC and LDO

•

Temperature sensor with programmable trip points

•

GPC hardware power management controller

The i.MX RT1050 processors support the following system debug:

•

Arm CoreSight debug and trace architecture

•

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

•

Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse

Security functions are enabled and accelerated by the following hardware:

•

High Assurance Boot (HAB)

•

Data Co-Processor (DCP):

— AES-128, ECB, and CBC mode

— SHA-1 and SHA-256

— CRC-32

•

Bus Encryption Engine (BEE)

— AES-128, ECB, and CTR mode

— On-the-fly QSPI Flash decryption

•

True random number generation (TRNG)

•

Secure Non-Volatile Storage (SNVS)

— Secure real-time clock (RTC)

— Zero Master Key (ZMK)

•

Secure JTAG Controller (SJC)

NOTE

The actual feature set depends on the part numbers as described in Table 1.

Functions such as display and camera interfaces, connectivity interfaces,

and security features are not offered on all derivatives.

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