RT1050 datasheet(8/110 Pages) NXP

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i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020

NXP Semiconductors

Architectural overview

The following subsections provide an architectural overview of the i.MX RT1050 processor system.

2.1

Block diagram

Figure 2 shows the functional modules in the i.MX RT1050 processor system1.

Figure 2. i.MX RT1050 system block diagram

1. Some modules shown in this block diagram are not offered on all derivatives. See Table 1 for details.

Internal Memory

512 KB OCRAM

shared with TCM

96 KB ROM

Multimedia

Connectivity

eMMC 4.5 / SD 3.0 x2

8 x 8 Keypad

External Memory

I2C x4

UART x8

S/PDIF Tx / Rx

GPIO

SPI x4

ADC

System Control

Secure JTAG

PLL / OSC

RTC and Reset

Enhanced DMA

IOMUX

GP Timer x6

CPU Platform

Arm Cortex-M7

32 KB I-cache

32 KB D-cache

FPU

FlexSPI (dual-channel QuadSPI

External Memory Controller

8-bit / 16-bit SDRAM

Parallel NOR FLASH

NAND FLASH

PSRAM

MPU

NVIC

Up to 512 KB TCM

FlexCAN x2

USB 2.0 OTG with PHY x2

10 / 100 ENET

with IEEE 1588 x1

ADC x2 (20-Channel)

ACMP x4

8 / 16 / 24-bit Parallel CSI

24-bit Parallel LCD

Arm Cortex-M7

32 KB I-cache

32 KB D-cache

FPU

MPU

NVIC

Up to 512 KB TCM

PXP

2D Graphics Acceleration

Resize, CSC, Overlay, Rotation

Quadrature ENC x4

QuadTimer

FlexPWM

Watch Dog x4

Power Management

DCDC

LDO

Temp Monitor

Security

Ciphers and RNG

Secure RTC

eFuse

HAB

I2S / SAI x3

(4-Channel) x4

NAND and NOR, Octal Flash, and RAM)

(8-Channel) x4

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