AS7000 datasheet(58/92 Pages) AMSCO

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ams Datasheet

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[v1-12] 2018-Feb-26

AS7000 − Detailed Description

15:12

adc_clock

ADC clock divider: The ADC clock is freely configurable.

Note that values other than 4MHz, 2MHz, 1MHz and

500kHz will make the resulting timing very confusing for

the human observer.

Setting

Periods

kHz

125

8000

250

4000

375

2666

500

2000

410

625

1600

512

750

1333

614

875

1142

716

1000

818

1125

888

920

1250

800

1375

727

1500

666

1625

615

1750

571

1875

533

2000

500

adc_calibration

To activate self calibration, this bit must be asserted, and

an ADC “conversion” has to be started in manual mode

(man_mode=1) by asserting seq_start. It is suggested to

let the CPU sleep and wait for the ADC interrupt. Also, a

slow ADC clock should be used.

adc_interleave

Interleave mode

9adc_en

0...Reset ADC

1...Enable ADC

Warning: In reset state the ADC clears its calibration data.

Re-calibration is necessary next time it is enabled again.

0xa4: AFE_ADC_CFG

Field

Name

Rst

Type

Description

AS7000 Datasheet(PDF) 58 Page - ams AG

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