June 2005

ASM2I99456

rev 0.2

3.3V/2.5V LVCMOS Clock Fanout Buffer

8 of 14

Notice: The information in this document is subject to change without notice.

GND

The time from the output controlled edge to the

non-controlled edge, divided by the time output

controlled edge, expressed as a percentage.

2.4

1.8V

0.55

0.6V

Figure 5. Output Transition Time Test Reference

PCLK

PCLK

GND

Figure 7. Output Duty Cycle (DC)

GND

GND

The pin-to-pin skew is defined as the worst case

difference in propagation delay between any similar

delay path within a single device

2.4

1.8V

0.55

0.6V

Figure 9. Output Transition Time Test Reference

Differential

Pulse Generator

Z=50

Ω

Figure 4. PCLK ASM2I99456 AC Test Reference for VCC = 3.3V and VCC = 2.5V

ASM2I99456 DUT