PMS133 datasheet(77/106 Pages) PADAUK

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PMS133/PMS134

8bit OTP MCU with 12-bit ADC

Page 77 of 106

PDK-DS-PMS133/134-EN_V103 – Nov. 13, 2018

6.30. Comparator Selection Register (gpcs), IO address = 0x2c

Bit

Reset

R/W

Description

Comparator output enable (to PA0).

0 / 1 : disable / enable

Reserved.

Selection of high range of comparator.

Selection of low range of comparator.

3 - 0

0000

Selection the voltage level of comparator.

west) ~ 1111 (highest)

6.31. Timer2 Control Register (tm2c), IO address = 0x30

Bit

Reset

R/W

Description

7 - 4

0000

R/W

Timer2 clock selection.

0000 : disable

0001 : CLK

0010 : IHRC or IHRC *2 (by code option TMx_source)

0011 : EOSC

0100 : ILRC

0101 : comparator output (ICE does NOT Support.)

1000 : PA0 (rising edge)

1001 : ~PA0 (falling edge)

1010 : PB0 (rising edge)

1011 : ~PB0 (falling edge)

1100 : PA4 (rising edge)

1101 : ~PA4 (falling edge)

Others: reserved

Notice: In ICE mode and IHRC is selected for Timer2 clock, the clock sent to Timer2 does

NOT be stopped, Timer2 will keep counting when ICE is in halt state.

3 - 2

R/W

Timer2 output selection.

00 : disable

01 : PB2

10 : PA3

11 : PB4

R/W

Timer2 mode selection.

0 / 1 : period mode / PWM mode

R/W

Enable to inverse the polarity of Timer2 output.

0 / 1: disable / enable

6.32. Timer2 Counter Register (tm2ct), IO address = 0x31

Bit

Reset

R/W

Description

7 - 0

0x00

R/W

Bit [7:0] of Timer2 counter register.

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