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FS6500 Datasheet(PDF) 9 Page - NXP Semiconductors

Part # FS6500
Description  Safety Power System Basis Chip with CAN FD and LIN
PDF  20 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FS6500 Datasheet(HTML) 9 Page - NXP Semiconductors

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NXP Semiconductors
FS6500, FS4500
Safety Power System Basis Chip with CAN FD and LIN Transceivers
FS6500-FS4500SDS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2017. All rights reserved.
Short data sheet: advance information
Rev. 1.0 — 14 December 2017
9 / 20
Pin
Symbol
Type
Definition
20
TXD
D_IN
Transceiver input from the MCU which controls the state of the CAN bus. Internal pull-
up to VDDIO.
If CAN function is not used, this pin must be left open.
21
RXD
D_OUT
Receiver output which reports the state of the CAN bus to the MCU
If CAN function is not used, this pin must be left open
TXDL
D_IN
Transceiver input from the MCU controlling the state of the LIN bus. Internal pull-up to
VDDIO.
or VPU_FS
A_OUT
Pull-up output for FS1B function
22
LIN and FS1B functions are exclusive. The differentiation is made by part numbers. When LIN is available, FS1B is not,
and vice versa. If neither LIN, nor FS1B functions are used, this pin must be left open.
23
RXDL
D_OUT
Receiver output reporting the state of the LIN bus to the MCU.
If LIN function is not used, this pin must be left open.
24
RSTB
D_OUT
This output is asserted low when the safety block reports a failure. The main function is
to reset the MCU. Reset input voltage is also monitored in order to detect external reset
and fault condition. Open drain structure.
25
MISO
D_OUT
SPI bus. Master input slave output
26
MOSI
D_IN
SPI bus. Master output slave input
27
SCLK
D_IN
SPI Bus. Serial clock
28
NCS
D_IN
Not chip select (active low)
29
INTB
D_OUT
This output pin generates a low pulse when an Interrupt condition occurs. Pulse
duration is configurable. Internal pull-up to VDDIO.
30
VDDIO
A_IN
Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.
31
SELECT
D_IN
Hardware selection pin for VAUX and VCCA output voltages
32
FB_CORE
A_IN
VCORE voltage feedback. Input of the error amplifier.
33
COMP_COR
E
A_OUT
Compensation network. Output of the error amplifier.
For FS4500 series, this pin must be left open (NC).
34
VCORE_SNS A_IN
VCORE input voltage sense
SW_CORE
A_OUT
VCORE output switching point for FS6500 series
35
or VCORE
A_OUT
VCORE output voltage for FS4500 series
36
BOOT_COR
E
A_IN/OUT
Bootstrap capacitor for VCORE internal NMOS gate drive.
For FS4500 series, this pin must be left open (NC).
37
VPRE
A_IN
VPRE input voltage sense
38
VAUX
A_OUT
VAUX output voltage. External PNP ballast transistor. Collector connection
39
VAUX_B
A_OUT
VAUX voltage regulator. External PNP ballast transistor. Base connection
40
VAUX_E
A_OUT
VAUX voltage regulator. External PNP ballast transistor. Emitter connection
41
VCCA_E
A_OUT
VCCA voltage regulator. External PNP ballast transistor. Emitter connection
42
VCCA_B
A_OUT
VCCA voltage regulator. External PNP ballast transistor. Base connection
43
VCCA
A_OUT
VCCA output voltage. External PNP ballast transistor. Collector connection
44
GATE_LS
A_OUT
Low-side MOSFET gate drive for non-inverting buck-boost configuration
45
DGND
GROUND
Digital ground connection
46
BOOT_PRE
A_IN/OUT
Bootstrap capacitor for the VPRE internal NMOS gate drive
47
SW_PRE2
A_OUT
Second pre-regulator output switching point
48
SW_PRE1
A_OUT
First pre-regulator output switching point



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