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FS6500 Datasheet(PDF) 11 Page - NXP Semiconductors |
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FS6500 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 20 page ![]() NXP Semiconductors FS6500, FS4500 Safety Power System Basis Chip with CAN FD and LIN Transceivers FS6500-FS4500SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved. Short data sheet: advance information Rev. 1.0 — 14 December 2017 11 / 20 Symbol Ratings Value Unit Notes ESD voltage VESD-HBM1 VESD-HBM2 VESD-HBM3 VESD-HBM4 Human body model (JESD22/A114) – 100 pF, 1.5 kΩ • All pins • VSUP1,2,3, VSENSE, VAUX, IO_0,4, FS0B, FS1B, DEBUG • CANH, CANL • LIN ±2.0 ±4.0 ±6.0 ±8.0 kV kV kV kV VESD-CDM1 VESD-CDM2 Charge device model (JESD22/C101): • All pins • Corner pins ±500 ±750 V V System level ESD (gun test) • VSUP1, 2, 3, VSENSE, VAUX, IO_0, 4, 5, FS0B, FS1B VESD-GUN1 330 Ω/150 pF unpowered according to IEC61000-4-2 ±8.0 kV VESD-GUN2 330 Ω/150 pF unpowered according to OEM LIN, CAN, FLexray Conformance ±8.0 kV VESD-GUN3 2.0 kΩ/150 pF unpowered according to ISO10605.2008 ±8.0 kV VESD-GUN4 2.0 kΩ/330 pF powered according to ISO10605.2008 • CANH, CANL ±8.0 kV VESD-GUN5 330 Ω/150 pF unpowered according to IEC61000-4-2 ±15.0 kV VESD-GUN6 330 Ω/150 pF unpowered according to OEM LIN, CAN, FLexray conformance ±12.0 kV VESD-GUN7 2.0 kΩ/150 pF unpowered according to ISO10605.2008 ±15.0 kV VESD-GUN8 2.0 kΩ/330 pF powered according to ISO10605.2008 • LIN ±12.0 kV VESD-GUN9 330 Ω/150 pF unpowered according to IEC61000-4-2: ±12.0 kV VESD-GUN10 330 Ω/150 pF unpowered according to OEM LIN, CAN, flexray conformance ±12.0 kV VESD-GUN11 2.0 kΩ/150 pF unpowered according to ISO10605.2008 ±12.0 kV VESD-GUN12 2.0 kΩ/330 pF powered according to ISO10605.2008 ±12.0 kV [2] Thermal ratings TA Ambient temperature –40 to 125 °C TJ Junction temperature –40 to 150 °C TSTG Storage temperature –55 to 150 °C Thermal resistance RθJA Thermal resistance junction to ambient 30 °C/W [3] RθJCTOP Thermal resistance junction to case top 23.8 °C/W [4] RθJCBOTTOM Thermal resistance junction to case bottom 0.9 °C/W [5] [1] All VSUPs (VSUP1/2/3) must be connected to the same supply [2] Compared to AGND [3] Per JEDEC JESD51-6 with the board (JESD51-7) horizontal [4] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1). [5] Thermal resistance between the die and the solder pad on the bottom of the packaged based on simulation without any interface resistance. |
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