MIC23156 datasheet(19/32 Pages) MICROCHIP

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DS20005919A-page 19

MIC23156

5.9

I2C Interface

Figure 5-4 shows the communications required for

write and read operations via the I2C interface. The

black lines show master communications and the red

lines show the slave communications. During a write

operation, the master must drive SDA and SCL for all

stages, except the Acknowledgment (A) stage shown

in red, which are provided by the slave (MIC23156).

The read operation begins first with a dataless write to

select the register address from which to read. A restart

sequence is issued, followed by a read command and

a data read.

The MIC23156 responds to a slave address of Hex 0xB6

and 0xB7 for write and read operations, respectively,

or binary 1011011x (where ‘x’ is the read/write bit,

= write, 1 = read).

The register address is eight bits wide and carries the

address of the MIC23156 register to be operated upon.

Only the lower three bits are used.

FIGURE 5-4:

Required Communications

for Read/Write Operations via I2C Interface.

5.10

I2C Register Summary

There are three I2C Read/Write registers that are 8 bits

in length. All registers are reset to a zero state when-

ever EN

 0.5V and set (reset) to their default values on

the transition of EN

 1.5V. All registers are accessible

by I2C.

TABLE 5-2:

5.11

Enable/Status Register (001b/01h)

The Enable/Status register is written to enable the out-

put regulator (BUCK_EN) and Soft Start Extension

mode (SSL). It is read to interrogate the status of Ther-

mal Shutdown (TSD), Undervoltage Lockout (UVLO)

and Power Good (PGOOD) status of the regulator. See

5.12

Buck Register 1 (010b/02h) and

Buck Register 2 (011b/03h)

These registers are written to set the output voltage to

any one of 170 levels in 10 mV steps. Values above

decimal 170 are equivalent to setting the register

to 170. The two registers correspond to one of two

states, which is selectable by the VSEL input pin. This

allows the regulator to be quickly switched between

two voltage levels (e.g., enabled and standby). When

VSEL = 0, the output voltage is controlled by BUCK_OUT1

(REG2).

When VSEL = 1, then the output voltage is

controlled by BUCK_OUT2 (REG3). See Register 5-2

and Register 5-3 for additional information.

SDA

SCL

SLAVE

ADDRESS

DATA

SLAVE

ADDRESS

S = START

= WRITE

A = ACKNOWLEDGE

SDA

SCL

SLAVE

ADDRESS

DATA

WRITE PROTOCOL

READ PROTOCOL

Sr = RESTART

R = READ

P = STOP

1011011 0

R A

1011011 0

1011011 1 0

Reg.

—

TSD

UVLO

PGOOD

BUCK_OUT1

BUCK_OUT2

Reg.

—

SSL

BUCK_EN

BUCK_OUT1

BUCK_OUT2

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