MIC23156 datasheet(14/32 Pages) MICROCHIP

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MIC23156

DS20005919A-page 14

 2017 Microchip Technology Inc.

4.0

FUNCTIONAL DESCRIPTION

FIGURE 4-1:

Functional Block Diagram.

4.1

PVIN

The Power Input Supply (PVIN) pin provides power to

the internal MOSFETs for the Switch mode regulator

section. The PVIN operating range is 2.7V to 5.5V, so an

input capacitor with a minimum voltage rating of 6.3V is

recommended. Due to the high switching speed, a mini-

mum 2.2 µF bypass capacitor, placed close to PVIN and

the Power Ground (PGND) pin, is required.

4.2

AVIN

Analog VIN (AVIN) pin provides power to the internal

control and analog supply circuitry. AVIN must be tied to

PVIN through a 10 RC filter. Careful layout should be

considered to ensure that any high-frequency switch-

ing noise caused by PVIN is reduced before reaching

AVIN. A 2.2 µF capacitor, as close to AVIN as possible,

is recommended.

4.3

A logic high signal on the Enable pin activates the out-

put voltage of the device. A logic low signal on the

Enable pin deactivates the output and reduces supply

current to 0.1 µA. Do not leave the EN pin floating.

MIC23156 features external soft start circuitry via the

Soft Start (SS) pin that reduces inrush current and

prevents the output voltage from overshooting when

EN is driven logic high. Do not leave the EN pin floating.

4.4

The Switch (SW) pin connects directly to one end of the

inductor and provides the current path during switching

cycles. The other end of the inductor is connected to the

SNS pin, output capacitor and the load. Due to the

high-speed switching on this pin, the Switch node should

be routed away from sensitive nodes whenever possible.

4.5

SNS

The Sense (SNS) pin is connected to the output of the

device to provide feedback to the control circuitry. The

SNS connection should be placed close to the output

capacitor.

4.6

AGND

The Analog Ground (AGND) pin is the ground path for

the biasing and control circuitry. The current loop for

the signal ground should be separate from the Power

Ground (PGND) loop.

4.7

PGND

The Power Ground (PGND) pin is the ground path for

the high current in PWM mode. The current loop for

the power ground should be as small as possible and

separate from the Analog Ground (AGND) loop, as

applicable.

PGND

SNS

PGOOD

SEL

SCL

SDA

I2C

CONTROL LOGIC:

I2C AND DAC

ON/tOFF

TIMER

DRIVER/

CURRENT LIMIT

ERROR

AMPLIFIER

REF

AGND

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