L64734 datasheet(39/48 Pages) LSI

39 / 48 page

L64733/L64734 Tuner and Satellite Receiver Chipset

The numbers in the ﬁrst column of Table 11 refer to the timing

parameters shown in the preceding ﬁgures. All parameters in the timing

tables apply for TA = 0 ˚C to 70 ˚C and a capacitive load of 15 pF.

Table 11

L64734 AC Timing Parameters

Parameter

Description

Min

Max

Units

tCYCLE

Clock Cycle for PCLK

11.1

33.31

1. Minimum Fs (sampling clock = 30 MHz).

tPWH

Clock Pulse Width HIGH

–

tPWL

Clock Pulse Width LOW

–

Input Setup Time to CLK

–

Input Hold to CLK

–

tODS

Output Delay from PCLK, serial mode

tODP

Output Delay from BCLKOUT, parallel

mode

–

PCLK

cycles

tRWH

Reset Pulse Width HIGH

–

CLK

cycles

tWK

Wake-Up Time

280

–

CLK

cycles

tDLY

Delay from COEn

–

tCYCLE_PS Clock Cycle for PSOUTp, PSOUTn

clock

tPWH_PS

PSOUT Clock Pulse Width HIGH

–

tPWL_PS

PSOUT Clock Pulse Width LOW

–

tOD_PS

Output Delay from PSOUT

8.5

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