1.

General description

The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface

with a GTL

−/GTL/GTL+ bus.

The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or

as a LVTTL to GTL interface.

The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or

5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.

The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used

in higher voltage open-drain output applications.

2.

Features

−/GTL/GTL+ sampling receiver or as a LVTTL to

GTL

−/GTL/GTL+ driver

JESD22-A115, and 1000 V CDM per JESD22-CC101

3.

Quick reference data

GTL2014

4-bit LVTTL to GTL transceiver

Rev. 01 — 19 May 2005

Product data sheet

Table 1:

Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

propagation delay; An-to-Bn

-

2.8

-

ns

-

3.4

-

ns

propagation delay; Bn-to-An

-

5.2

-

ns

-

4.9

-

ns

input capacitance on pin DIR;

A-to-B or B-to-A

-

2

2.5

pF

input/output capacitance; A-to-B

outputs disabled;

-

4.6

6.0

pF

input/output capacitance; B-to-A

-

3.4

4.3

pF