ED14R126-12AMBTEL datasheet(39/51 Pages) EOREX

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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns

Symbol

DDR3-1066

DDR3-1333

DDR3-1600

Unit

7-7-7

9-9-9

11-11-11

tCK

1.875

1.5

1.25

nCK

nRCD

nCK

nRC

nCK

nRAS

nCK

nRP

nCK

nFAW

1KB page size

nCK

2KB page size

nCK

nRRD

1KB page size

nCK

2KB page size

nCK

nRFC -512Mb

nCK

nRFC-1 Gb

nCK

nRFC- 2 Gb

107

128

nCK

nRFC- 4 Gb

139

174

208

nCK

nRFC- 8 Gb

187

234

280

nCK

Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol

Description

IDD0

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and

PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;

DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-

fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.

IDD1

Operating One Bank Active-Precharge Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,

RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:

stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and

RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.

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