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ADS7822EB Datasheet(PDF) 11 Page - Texas Instruments |
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ADS7822EB Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 20 page  ADS7822 11 SBAS062A www.ti.com SYMBOL DESCRIPTION MIN TYP MAX UNITS tSMPL Analog Input Sample Time 1.5 2.0 Clk Cycles tCONV Conversion Time 12 Clk Cycles tCYC Throughput Rate 75 kHz tCSD CS Falling to 0 ns DCLOCK LOW tSUCS CS Falling to 30 ns DCLOCK Rising thDO DCLOCK Falling to 15 ns Current DOUT Not Valid tdDO DCLOCK Falling to Next 130 200 ns DOUT Valid tdis CS Rising to DOUT Tri-State 40 80 ns ten DCLOCK Falling to DOUT 75 175 ns Enabled tf DOUT Fall Time 90 200 ns tr DOUT Rise Time 110 200 ns periods, DOUT will output the conversion result, most signifi- cant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data but in a least significant bit first format. After the most significant bit (B11) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. DATA FORMAT The output data from the ADS7822 is in straight binary format as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I. TABLE I. Timing Specifications (VCC = 2.7V and above, –40 °C to +85°C. A falling CS signal initiates the conversion and data transfer. The first 1.5 to 2.0 clock periods of the conversion cycle are used to sample the input signal. After the second falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 12 DCLOCK DESCRIPTION ANALOG VALUE Full Scale Range VREF Least Significant VREF/4096 Bit (LSB) BINARY CODE HEX CODE Full Scale VREF –1 LSB 1111 1111 1111 FFF Midscale VREF/2 1000 0000 0000 800 Midscale – 1 LSB VREF/2 – 1 LSB 0111 1111 1111 7FF Zero 0V 0000 0000 0000 000 DIGITAL OUTPUT STRAIGHT BINARY TABLE II. Ideal Input Voltages and Output Codes. D OUT 1.4V Test Point 3k Ω 100pF C LOAD Load Circuit for t dDO, tr, and tf Voltage Waveforms for D OUT Rise and Fall Times, tr, tf Voltage Waveforms for D OUT Delay Times, tdDO Voltage Waveforms for t dis NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Voltage Waveforms for t en Load Circuit for t dis and ten t r D OUT V OH V OL t f D OUT Test Point t dis Waveform 2, ten V CC t dis Waveform 1 100pF C LOAD 3k Ω t dis CS/SHDN DOUT Waveform 1(1) DOUT Waveform 2(2) 90% 10% V IH 1 B11 2 t en CS/SHDN DCLOCK V OL D OUT t dDO D OUT DCLOCK V OH V OL V IL t hDO |
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