RA2A1 datasheet(4/100 Pages) RENESAS

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R01DS0354EJ0110 Rev.1.10

Page 4 of 100

Mar 16, 2020

RA2A1 Datasheet

1. Overview

Resets

13 resets:

 RES pin reset

 Power-on reset

 Independent watchdog timer reset

 Watchdog timer reset

 Voltage monitor 0 reset

 Voltage monitor 1 reset

 Voltage monitor 2 reset

 SRAM parity error reset

 SRAM ECC error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 CPU stack pointer error reset

 Software reset.

See section 6, Resets in User’s Manual.

Low Voltage Detection (LVD)

The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin and

the detection level can be selected using a software program. See section 8, Low Voltage

Detection (LVD) in User’s Manual.

Clocks

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 IWDT-dedicated on-chip oscillator

 Clock out support.

See section 9, Clock Generation Circuit in User’s Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock to be used as a

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.

When measurement is complete or the number of pulses within the time generated by the

measurement reference clock is not within the allowable range, an interrupt request is

generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s

Manual.

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module. The ICU also controls NMI interrupts. See section 13, Interrupt Controller Unit (ICU) in

User’s Manual.

Key Interrupt Function (KINT)

A key interrupt can be generated by setting the Key Return Mode Register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 19, Key Interrupt Function

(KINT) in User’s Manual.

Low power modes

Power consumption can be reduced in multiple ways, such as by setting clock dividers,

stopping modules, selecting power control mode in normal operation, and transitioning to low

power modes. See section 11, Low Power Modes in User’s Manual.

The register write protection function protects important registers from being overwritten due to

software errors. See section 12, Register Write Protection in User’s Manual.

Memory Protection Unit (MPU)

Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 15, Memory Protection Unit (MPU) in User’s Manual.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. A

refresh-permitted period can be set to refresh the counter and used as the condition to detect

when the system runs out of control. See section 24, Watchdog Timer (WDT) in User’s

Manual.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. The IWDT provides functionality to reset

the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the

timer operates with an independent, dedicated clock source, it is particularly useful in returning

the MCU to a known state as a fail-safe mechanism when the system runs out of control. The

IWDT can be triggered automatically on a reset, underflow, refresh error, or by a refresh of the

count value in the registers. See section 25, Independent Watchdog Timer (IWDT) in User’s

Manual.

Table 1.3

System (2 of 2)

Feature

Functional description

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