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UPD17P136ACT Datasheet(PDF) 25 Page - NEC |
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UPD17P136ACT Datasheet(HTML) 25 Page - NEC |
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25 / 292 page  CHAPTER 1 GENERAL DESCRIPTION 6 (2) Program memory write/verify mode 28-pin plastic shrink DIP (400 mil) µPD17P136ACT, 17P137ACT 28-pin plastic SOP (375 mil) µPD17P136AGT, 17P137AGT Caution ( ) represents processing of the pins which are not used in program memory write/verify mode. L : Connect to GND via pull-down resistor one by one. RESET : Set the same electric potential as VDD in program memory write/verify mode. RESET pin is also used for system reset input before setting program memory write/verify mode. Therefore, RESET pin should be set to the same electric potential as VDD 10 µs or later than that of VDD pin (For details, refer to CHAPTER 18 ONE-TIME PROM WRITING/VERIFYING). Open : Do not connect anything. VDD : Connect to VDD directly. (VDD) 1 (L) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MD3 MD2 MD1 MD0 D7 D6 D5 D4 D3 D2 D1 D0 GND RESET VPP CLK VDD (L) (Open) |
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