UPD17P136ACT datasheet(66/292 Pages) NEC

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CHAPTER 7 SYSTEM REGISTER (SYSREG)

7.5 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP)

7.5.1 Index Register (IX)

IX is used for address modification of the data memory. The difference between IX and MP is that IX modifies an

address specified by a bank and operand m.

IX is allocated to a total of 12 bits of system register addresses 7AH (IXH), 7BH (IXM), and 7CH (IXL), as shown

in Figure 7-8. Actually, however, only 11 bits, the low-order 3 bits of IXH, IXM, and IXL, function as IX. An index register

enable flag (IXE) which enables address modification by IX is assigned to the least significant bit of PSW.

When IXE = 1, the address of the data memory specified by operand m is not m, but the result of ORing between

m and IXM through IXL. The bank specified at this time is also indicated by ORing BANK and IXH.

Remark IXH of the

µPD17134A subseries is fixed to “0”, and the bank is not modified even when IXE = 1 (to prevent

a bank other than 0 from being used).

7.5.2 Data Memory Row Address Pointer (Memory Pointer: MP)

MP is used for address modification of the data memory. The difference between IX and MP is that MP modifies

the row address of an address indirectly specified by bank and operand @r.

MPH and IXH and MPL and IXM are assigned to the same address (addresses 7AH and 7BH of the system register)

as shown in Figure 7-8. Actually, however, the low-order 3 bits of MPH and MPL, or a total of 7 bits, function as MP.

A memory pointer enable flag (MPE) which enables address modification by MP is assigned to the most significant

bit of MPH.

When MPE = 1, the bank and row address of the data memory indirectly specified by operand @r are not BANK

and mR, but the address specified by MP (the column address is specified by the contents of r independently of MPE).

At this time, the low-order 3 bits of MPH and the most significant bit of MPL indicate BANK, and the low-order 3 bits

of MPL indicate a row address.

Remark The low-order 3 bits of MPH and most significant bit of MPL of the

µPD17134A subseries are fixed to

“0”, and bank 0 is always specified even when MPE = 1 (to prevent a bank other than 0 from being used).

Figure 7-8. Index Register Configuration

00000000000

0000

7AH

7BH

7CH

7FH

Address

Initial value when reset

Index register (IX)

Memory pointer (MP)

IXH

MPH

IXM

MPL

IXL

Bit

Name

Symbolic name

Flag name

Data

000

(MP)

(IX)

PSW

Low-order 4

bits of program

status word

(PSWORD)

UPD17P136ACT Datasheet(PDF) 66 Page - NEC

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