UPD17P136ACT datasheet(15/292 Pages) NEC

15 / 292 page

- viii -

9-1

Register File Configuration ...................................................................................................................... 69

9-2

Relationship Between the Register File and Data Memory ................................................................... 70

9-3

Accessing the Register File Using the PEEK and POKE Instructions .................................................. 72

9-4

Control Register Configuration ................................................................................................................ 75

10-1

Allocation of the Data Buffer ................................................................................................................... 77

10-2

Data Buffer Configuration ........................................................................................................................ 77

10-3

Relationship Between the Data Buffer and Peripheral Hardware ......................................................... 78

11-1

ALU Configuration .................................................................................................................................... 84

12-1

Input/Output Switching by Group I/O .................................................................................................... 106

12-2

Port Control Register of Bit I/O ............................................................................................................. 107

12-3

Specifying Pull-Up Resistor Incorporation Using Software .................................................................. 109

13-1

Configuration of the 8-Bit Timer Counters ............................................................................................ 112

13-2

Timer 0 Mode Register .......................................................................................................................... 113

13-3

Timer 1 Mode Register .......................................................................................................................... 114

13-4

Setting Count Value to Modulo Register ............................................................................................... 116

13-5

Reading Count Value of Count Register ............................................................................................... 117

13-6

Error When Count Register Is Cleared to 0 During Counting ............................................................. 119

13-7

Error When Counting Is Started from Count Stop Status .................................................................... 120

13-8

Timer 0 Output Setting Register ............................................................................................................ 121

13-9

Basic Interval Timer Configuration ........................................................................................................ 122

13-10

BTM Mode Register ............................................................................................................................... 123

13-11

Watchdog Timer Mode Register ............................................................................................................ 124

13-12

Timing Chart of Watchdog Timer (with WDTRES Flag Used) ............................................................. 126

13-13

Block Diagram of the A/D Converter ..................................................................................................... 128

13-14

A/D Converter Control Register ............................................................................................................ 130

13-15

Setting a Value in the 8-Bit Data Register (ADCR) .............................................................................. 132

13-16

Reading Values from the 8-bit Data Register (ADCR) ......................................................................... 133

13-17

Relationship between the Analog Input Voltage and Digital Conversion Result ................................ 134

13-18

Using the Successive Mode for the A/D Converter .............................................................................. 136

13-19

A/D Conversion Timing in the Continuous Mode ................................................................................. 137

13-20

Using the Single Mode for the A/D Converter ...................................................................................... 139

13-21

Single Mode Operation (Comparison) Timing ...................................................................................... 140

13-22

Block Diagram of the Serial Interface ................................................................................................... 142

13-23

Timing of 8-Bit Transmission and Reception Mode (Simultaneous Transmission and Reception) .. 143

13-24

Timing of the Clock Synchronization 8-Bit Reception Mode (SO Pin Output High Impedance) ........ 144

13-25

Serial Interface Control Register ........................................................................................................... 145

13-26

Setting a Value in the Shift Register ..................................................................................................... 147

13-27

Reading a Value from the Shift Register .............................................................................................. 148

LIST OF FIGURES (2/3)

Figure No.

Title

Page

UPD17P136ACT Datasheet(PDF) 15 Page - NEC

UPD17P136ACT Datasheet(HTML) 15 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL