TMS320VC5409A datasheet(3/98 Pages) TI

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Contents

TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

Revision History

........................................................................................................................... 2

TMS320VC5409A Features

.................................................................................................... 9

Introduction

....................................................................................................................... 10

2.1

Description

.................................................................................................................. 10

2.2

Pin Assignments

............................................................................................................ 10

2.2.1

Terminal Assignments for the GGU Package

............................................................... 10

2.2.2

Pin Assignments for the PGE Package

...................................................................... 12

2.3

Signal Descriptions

......................................................................................................... 13

Functional Overview

........................................................................................................... 17

3.1

Memory

...................................................................................................................... 17

3.1.1

Data Memory

.................................................................................................... 17

3.1.2

Program Memory

............................................................................................... 18

3.1.3

Extended Program Memory

................................................................................... 18

3.2

On-Chip ROM With Bootloader

........................................................................................... 18

3.3

On-Chip RAM

............................................................................................................... 19

3.4

On-Chip Memory Security

................................................................................................. 19

3.5

Memory Map

................................................................................................................ 20

3.5.1

Relocatable Interrupt Vector Table

........................................................................... 20

3.6

On-Chip Peripherals

....................................................................................................... 22

3.6.1

Software-Programmable Wait-State Generator

............................................................. 22

3.6.2

Programmable Bank-Switching

............................................................................... 23

3.6.3

Bus Holders

..................................................................................................... 25

3.7

Parallel I/O Ports

........................................................................................................... 25

3.7.1

Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)

......................................................... 25

3.7.2

HPI Nonmultiplexed Mode

..................................................................................... 26

3.8

Multichannel Buffered Serial Ports (McBSPs)

.......................................................................... 27

3.9

Hardware Timer

............................................................................................................ 30

3.10

Clock Generator

............................................................................................................ 30

3.11

Enhanced External Parallel Interface (XIO2)

........................................................................... 32

3.12

DMA Controller

............................................................................................................. 35

3.12.1

Features

.......................................................................................................... 35

3.12.2

DMA External Access

.......................................................................................... 35

3.12.3

DMPREC Issue

................................................................................................. 36

3.12.4

DMA Memory Map

.............................................................................................. 38

3.12.5

DMA Priority Level

.............................................................................................. 39

3.12.6

DMA Source/Destination Address Modification

............................................................. 39

3.12.7

DMA in Autoinitialization Mode

............................................................................... 40

3.12.8

DMA Transfer Counting

........................................................................................ 40

3.12.9

DMA Transfer in Doubleword Mode

.......................................................................... 41

3.12.10

DMA Channel Index Registers

.............................................................................. 41

3.12.11

DMA Interrupts

................................................................................................ 41

3.12.12

DMA Controller Synchronization Events

................................................................... 42

3.13

General-Purpose I/O Pins

................................................................................................. 43

3.13.1

McBSP Pins as General-Purpose I/O

........................................................................ 43

3.13.2

HPI Data Pins as General-Purpose I/O

...................................................................... 43

3.14

Device ID Register

......................................................................................................... 44

3.15

Memory-Mapped Registers

............................................................................................... 45

3.16

McBSP Control Registers and Subaddresses

.......................................................................... 47

3.17

DMA Subbank Addressed Registers

.................................................................................... 48

Contents

TMS320VC5409A Datasheet(PDF) 3 Page - Texas Instruments

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