TMS320VC5409A datasheet(22/98 Pages) TI

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3.6

On-Chip Peripherals

3.6.1

Software-Programmable Wait-State Generator

TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

The 5409A device has the following peripherals:

• Software-programmable wait-state generator

• Programmable bank-switching

• A host-port interface (HPI8/16)

• Three multichannel buffered serial ports (McBSPs)

• A hardware timer

• A clock generator with a multiple phase-locked loop (PLL)

• Enhanced external parallel interface (XIO2)

• A DMA controller (DMA)

The software wait-state generator of the 5409A can extend external bus cycles by up to fourteen machine

cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY

line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state

generator are automatically disabled. Disabling the wait-state generator clocks reduces the power

consumption of the 5409A.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs

of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to

five separate address ranges. This allows a different number of wait states for each of the five address

ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control

wait-state generator is initialized to provide seven wait states on all external memory accesses. The

SWWSR bit fields are shown in Figure 3-5 and described in Table 3-3.

XPA

I/O

Data

R/W-0

R/W-111

Data

Program

R/W-111

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address

0028h]

Table 3-3. Software Wait-State Register (SWWSR) Field Descriptions

BIT

FIELD

VALUE

DESCRIPTION

Extended program address control bit. XPA is used in conjunction with the program space fields (bits 0

XPA

through 5) to select the address range for program space wait states.

I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses

14-12

I/O

111

within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for

the base number of wait states.

Upper data space. The field value (0-7) corresponds to the base number of wait states for external

11-9

Data

111

data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a

multiplication factor of 1 or 2 for the base number of wait states.

Functional Overview

TMS320VC5409A Datasheet(PDF) 22 Page - Texas Instruments

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