 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320VC5409A Datasheet(PDF) 78 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320VC5409A Datasheet(HTML) 78 Page - Texas Instruments |
|
|
78 / 98 page  www.ti.com (n-2) Bit (n-1) (n-3) (n-2) Bit (n-1) (n-4) (n-3) (n-2) Bit (n-1) th(BCKRL-BDRV) tsu(BDRV-BCKRL) th(BCKRL-BDRV) tsu(BDRV-BCKRL) tsu(BDRV-BCKRL) th(BCKRL-BDRV) th(BCKRL-BFRH) tsu(BFRH-BCKRL) td(BCKRH-BFRV) td(BCKRH-BFRV) tr(BCKRX) tr(BCKRX) tw(BCKRXL) tc(BCKRX) tw(BCKRXH) (RDATDLY=10b) BDR (RDATDLY=01b) BDR (RDATDLY=00b) BDR BFSR (ext) BFSR (int) BCLKR TMS320VC5409A Fixed-PointDigital Signal Processor SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005 Table 5-21. McBSP Transmit and Receive Switching Characteristics (1) 5409A-120 5409A-160 PARAMETER UNIT MIN MAX tc(BCKRX) Cycle time, BCLKR/X BCLKR/X int 4P(2) ns tw(BCKRXH) Pulse duration, BCLKR/X high BCLKR/X int D – 1(3) D + 1(3) ns tw(BCKRXL) Pulse duration, BCLKR/X low BCLKR/X int C – 1(3) C + 1(3) ns BCLKR int – 3 3 ns td(BCKRH-BFRV) Delay time, BCLKR high to internal BFSR valid BCLKR ext 0 11 ns BCLKX int – 1 5 td(BCKXH-BFXV) Delay time, BCLKX high to internal BFSX valid ns BCLKX ext 2 10 BCLKX int 6 Disable time, BCLKX high to BDX high impedance following last data tdis(BCKXH-BDXHZ) ns bit of transfer BCLKX ext 10 BCLKX int – 1(5) 10 td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid DXENA = 0(4) ns BCLKX ext 2 20 BFSX int – 1(5) 7 Delay time, BFSX high to BDX valid td(BFXH-BDXV) ns ONLY applies when in data delay 0 (XDATDLY = 00b) mode BFSX ext 2 11 (1) CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P = 0.5 * processor clock (3) T = BCLKRX period = (1 + CLKGDV) * 2P C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even (4) The transmit delay enable (DXENA) feature of the McBSP is not implemented on the TMS320VC5409A. (5) Minimum delay times also represent minimum output hold times. Figure 5-21. McBSP Receive Timings 78 Electrical Specifications |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
