TMS320VC5409A datasheet(7/98 Pages) TI

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TMS320VC5409A

Fixed-PointDigital Signal Processor

SPRS140F – NOVEMBER 2000 – REVISED JANUARY 2005

List of Tables

2-1

Terminal Assignments

........................................................................................................... 11

2-2

Signal Descriptions

............................................................................................................... 13

3-1

Standard On-Chip ROM Layout

................................................................................................ 19

3-2

Processor Mode Status Register (PMST) Field Descriptions

............................................................... 21

3-3

Software Wait-State Register (SWWSR) Field Descriptions

................................................................ 22

3-4

Software Wait-State Control Register (SWCR) Field Descriptions

......................................................... 23

3-5

Bank-Switching Control Register (BSCR) Field Descriptions

............................................................... 24

3-6

Bus Holder Control Bits

.......................................................................................................... 25

3-7

Sample Rate Generator Clock Source Selection

............................................................................. 28

3-8

Receive Channel Enable Registers for Partitions A to H Field Descriptions

.............................................. 30

3-9

Transmit Channel Enable Registers for Partitions A to H Field Descriptions

............................................. 30

3-10

Clock Mode Settings at Reset

................................................................................................... 31

3-11

DMD Section of the DMMCRn Register

........................................................................................ 36

3-12

DMA Channel Enable Control Register (DMCECTL) Field Description

.................................................... 37

3-13

DMA Reload Register Selection

................................................................................................ 40

3-14

DMA Interrupts

.................................................................................................................... 41

3-15

DMA Synchronization Events

.................................................................................................... 42

3-16

DMA Channel Interrupt Selection

............................................................................................... 42

3-17

CPU Memory-Mapped Registers

................................................................................................ 45

3-18

Peripheral Memory-Mapped Registers for Each DSP Subsystem

......................................................... 45

3-19

McBSP Control Registers and Subaddresses

................................................................................. 47

3-20

DMA Subbank Addressed Registers

........................................................................................... 48

3-21

Interrupt Locations and Priorities

................................................................................................ 50

5-1

Input Clock Frequency Characteristics

......................................................................................... 56

5-2

Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options

........................................ 57

5-3

Divide-By-2 and Divide-By-4 Clock Options Timing Requirements

........................................................ 57

5-4

Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics

.................................................... 57

5-5

Multiply-By-N Clock Option Timing Requirements

............................................................................ 59

5-6

Multiply-By-N Clock Option Switching Characteristics

....................................................................... 59

5-7

Memory Read Timing Requirements

........................................................................................... 60

5-8

Memory Read Switching Characteristics

....................................................................................... 60

5-9

Memory Write Switching Characteristics

....................................................................................... 63

5-10

I/O Read Timing Requirements

................................................................................................. 65

5-11

I/O Read Switching Characteristics

............................................................................................. 65

5-12

I/O Write Switching Characteristics

............................................................................................. 67

5-13

Ready Timing Requirements for Externally Generated Wait States

....................................................... 68

5-14

Ready Switching Characteristics for Externally Generated Wait States

................................................... 68

5-15

HOLD and HOLDA Timing Requirements

..................................................................................... 71

5-16

HOLD and HOLDA Switching Characteristics

................................................................................. 71

List of Tables

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