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DP83241 Datasheet(PDF) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83241
Description  CDD Device (FDDI Clock Distribution Device)
PDF  20 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83241 Datasheet(HTML) 5 Page - National Semiconductor (TI)

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30 Pin Descriptions
Symbol
Pin
IO
Description
No
DVCC
16
Digital VCC Positive power supply for all the internal circuitry intended for operation at 5V g5% relative
to GND A bypass capacitor should be placed as close as possible across the DVCC and DGND pins
EXTVCC
28
External VCC Positive power supply for all the output buffers intended for operation at 5V g5% relative
to GND A bypass capacitor should be placed as close as possible across the EXTVCC and EXTGND
pins
DGND
15
Digital Ground
Internal circuit power supply return
EXTGND
1
External Ground
Output buffer power supply return
AGND
14
Analog Ground
Substrate ground used to ensure proper device biasing and isolation
AVCC
18
Analog VCC Positive power supply for the critical analog circuitry intended for a5V operation g5%
relative to Ground A bypass cap should be placed as close as possible between AVCC and AGND
XTL IN
8
I
External Crystal Oscillator Input
XTL IN can also be used as a CMOS compatible reference frequency
input for the PLL This input is selected when REF SEL is at a logical LOW level The component
connections required for oscillator operation are shown in the application diagrams
XTL OUT
6
External Crystal Oscillator Output
XTL OUT is not intended for use as a logic drive output pin
REF IN
5
I
Reference Input
TTL compatible input for use as the PLL’s phase comparator reference frequency
input when the REF SEL is at a logic HI level This input is for use in concentrator configurations where
there are multiple CDD devices at a given site requiring synchronization
FEEDBK IN
4
I
Feedback Input
TTL compatible input for use as the PLL’s phase comparator feedback input to close
the loop This input is intended to be driven from one of the LBCs (Local Byte Clocks) This input is
designed to provide the same frequency and within 2 ns of the same phase as REF IN when REF IN is in
active operation
REF SEL
9
I
Reference Select
TTL compatible input which selects either the crystal oscillator inputs XTL IN and
XTL OUT or the REF IN inputs as the reference frequency inputs for the PLL The crystal oscillator inputs
are selected when REF SEL is at a logic LOW level and the REF IN input is selected as the reference
frequency when REF SEL is at a logic HI level
FILTER
10
O
Filter
Low pass PLL loop filter pin A three element filter consisting of one capacitor in parallel with a
resistor and another capacitor should be connected between this pin and ground
VCO SEL
17
I
VCO Select
TTL compatible input used to select either the internal VCO or an external VCO through the
XVCO IN and XVCO INB pins The internal VCO is selected when the VCO SEL pin is at a logic HIGH
level and the external VCO is selected when at a logic LOW level
XVCO IN
13
I
External VCO Inputs
Differential inputs for use with an external VCO These inputs are DC biased to
approximately one half VCC and can be connected to either a full differential VCO or a single-ended
XVCO INB
12
VCO To use a single-ended VCO couple the signal into one of the inputs through a series low value
capacitor and bypass the other input to GND through a 001 mF capacitor When not in use ground one
input and let the other float
5



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