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DP83241 Datasheet(PDF) 16 Page - National Semiconductor (TI) |
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DP83241 Datasheet(HTML) 16 Page - National Semiconductor (TI) |
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16 / 20 page  50 Detailed Information (Continued) 53 LAYOUT RECOMMENDATIONS The part should be bypassed between the EXTVCC and EXTGND as close to the chip as possible (preferably un- der the chip using chip caps) The part should also be bypassed between the DVCC and DGND as close to the chip as possible The part should be bypassed between AVCC and AGND as close to the chip as possible No TTL logic lines should pass through the external crys- tal or filter circuitry areas to avoid the possibility of noise due to crosstalk The filter circuitry should be connected to Ground on an isolated branch off of the AGND pin The DVCC pin should be connected to VCC on an isolat- ed branch off of the EXTVCC pin preferably being con- nected through a ferrite bead or small inductor The AVCC pin should be connected to VCC on an isolat- ed branch off of the DVCC pin preferably being connect- ed through a ferrite bead or small inductor The external crystal circuitry should be connected to Ground on an isolated branch off of the DGND pin The DGND pin should be connected to Ground off of an isolated branch of the EXTGND pin connected through a ferrite bead or small inductor The AGND pin should be connected to Ground off of an isolated branch of the DGND pin connected through a ferrite bead or small inductor If the part is being driven by an external reference the XTL IN pin should be tied to either GND or VCC If using a multilayered board with dedicated VCC and Ground planes ensure that the external crystal circuitry has its own small isolated ground island that is connect- ed to the AGND DGND and EXTGND pins as described above See Figure 51 for component values For best performance tie the VCORST pin to AGND This drawing was done with convenience in mind TLF10385 – 15 Note Pin 7 need not be hooked up FIGURE 5-10 Recommended Layout 16 |
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