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GS9021 Datasheet(PDF) 6 Page - Gennum Corporation

Part # GS9021
Description  EDH Coprocessor
PDF  26 Pages
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Manufacturer  GENNUM [Gennum Corporation]
Direct Link  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS9021 Datasheet(HTML) 6 Page - Gennum Corporation

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DETAILED DESCRIPTION
The GS9021 EDH coprocessor consists of five major
blocks:
1. Data Input/Output Block (with automatic standard
detect)
2. Flywheel Block
3. EDH Block
4. Data Processing Block
5. Host Interface (HOSTIF) Block
The following convention is used to differentiate device pins
from HOST interface table bits.
LOGIC OPR (logic operator) gives the combinational
relationship (if one exists), between pins which also have a
corresponding HOST bit. This operator governs the signal
the GS9021 receives. The following is the list of possible
logic operators and their meaning.
1. DATA INPUT/OUTPUT BLOCK
1.1 Parallel Digital Video Data Inputs
Parallel digital video data is supplied to the GS9021 chip
via the DIN[9:0] input pins. The data is clocked into the
GS9021 by the rising edge of PCLKIN.
Eight input signal standards are supported: Composite,
4:2:2 Component with 13.5MHz Y sampling, 4:2:2 16 x 9
wide screen with 18 MHz Y sampling, and 4:4:4:4
Component Single Link with 13.5MHz Y sampling, all in
both NTSC and PAL formats (See Table 1). Both 8 and 10
bit inputs are supported. However, when using 8 bit data,
the 2 LSBs of the input must be tied to GND.
1.2 Parallel Clock Inputs
The PCLKIN pin is the input used to clock the video data
into the GS9021, and serves as the reference to which all
synchronous inputs and outputs are timed. The following
table shows which pins are synchronous with PCLKIN and
which are not. Timing for synchronous I/O is found in
Figures 1 and 2.
PIN
LOGIC OPR
HOSTIF
XX
YY
LOGIC OPR
MEANING
AND
XX AND YY
OR
XX OR YY
>
XX takes precedence over YY
<
YY takes precedence over XX
PIN
LOGIC OPR
HOST BIT
DOUT[9:0]
PIN
LOGIC OPR
HOST BIT
PCLKIN
SYNCHRONOUS
ASYNCHRONOUS
FL[4:0]
P[7:5]
S[1:0]
SCL/P4
FIFO_RESET
INTERRUPT
DOUT[9:0]
SDA/P3
F[2:0]
A[2:0]/P[2:0]
VR/W
HA/D
ANC_DATA
CS
BLANK_EN
FLAG_MAP
F_R/W
RESET
NO_EDH
CRC_MODE
STD[3:0]
VBLANKS/L
TRS_ERROR
HOSTIF_MODE
DIN[9:0]
FIFOE/S
FLYWDIS
BYPASS_EDH
SDO_MODE
ANC_CHKSM
CLIP_TRS



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