GS9021 datasheet(8/26 Pages) GENNUM

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The SWITCHFLYW control signal is used in applications

where the data input to the GS9021 is switched between

two synchronous signals. In this case, the two signals may

be slightly misaligned and would normally require the

flywheel to completely re-synchronize. In this scenario, the

re-synchronization time would be undesirable. Asserting the

SWITCHFLYW bit of the HOSTIF write table HIGH allows the

flywheel to re-synchronize to the new incoming signal at the

end of the switching line. For this functionality to operate

properly, the two signals must both be in the active picture

portion of the switching line at the time of the switch.

2.2 Accurate FVH Timing Signals

The F[2:0] signals indicate the current field of the video

data. Three F bits are necessary to accommodate the

composite PAL standard which has 8 fields. For component

standards only F0 is used to represent F = 0 or F = 1. The

F[2:0] bits are available on dedicated output pins and via

the HOSTIF read table. Figure 4a and 4b illustrate the

position of the F[2:0] transition within a line for component

and composite signals, respectively. The lines on which the

transitions occur conform to the SMPTE standards.

For component signals, the horizontal (H) signal is HIGH

during the horizontal blanking region of the output signal,

from EAV to SAV inclusive. For composite signals, the H

signal remains HIGH only for the 3FF, 000, 000, 000, and

TRSID words. Figure 4a and 4b illustrate the H output signal

timing for component and composite signals, respectively.

The vertical (V) signal timing is dependent on the incoming

video standard and the VBLANKS/L control signal. The

VBLANKS/L signal is available as an input pin and via the

HOSTIF write table and should be set to indicate the form of

the incoming data stream. This allows the flywheel to

correctly structure the V bit for flywheel synchronization,

TRS insertion, and TRS error indication.

For component based standards, the transition of the V

output signal within a line is shown in Figure 4a. The line on

which the V output signal transitions from HIGH to LOW is

summarized in the following table.

The lines on which the LOW to HIGH transition occurs

conform to the SMPTE standards.

For composite based standards, the V output signal is

asserted HIGH as described in the table below:

2.3 TRS Errors

The flywheel is also used to indicate TRS errors. These

errors are detected by comparing the TRS in the incoming

data stream with the expected TRS based on the internal

flywheel.

LOGIC OPR

HOST BIT

F[2:0]

VBLANKS/L

AND

VBLANKS/L

STANDARD

VBLANKS/L=1

VBLANKS/L=0

NTSC 4:2:2 Component

(13.5MHz Y sampling)

9/272

19/282

NTSC 4:2:2 16x9 Widescreen

(18MHz Y sampling)

9/272

19/282

NTSC 4:4:4:4 Single Link

(13.5MHz Y sampling)

9/272

19/282

PAL 4:2:2 Component

(13.5MHz Y sampling)

22/335

PAL 4:2:2 16x9 Widescreen

(18MHz Y sampling)

22/335

PAL 4:4:4:4 Single Link

(13.5MHz Y sampling)

22/335

VBLANKS/L=1

VBLANKS/L=0

NTSC

Composite

from Line 525/ Sample

768 to Line 9/ Sample

767 inclusive

AND

from Line 263/ Sample

313 to Line 272/

Sample 767 inclusive

from Line 525/ Sample

768 to Line 19/ Sample

767 inclusive

AND

from Line 263/ Sample

313 to Line 282/

Sample 767 inclusive

VBLANKS/L=1

VBLANKS/L=0

PAL

Composite

from Line 623/ Sample

382 to Line 5/ Sample

947 inclusive

AND

from Line 310/ Sample

948 to Line 317/

Sample 947 inclusive

from Line 623/ Sample

382 to Line 15/ Sample

947 inclusive

AND

from Line 310/ Sample

948 to Line 327/

Sample 947 inclusive

LOGIC OPR

HOST BIT

TRS_ERROR

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