F0448 Datasheet

© 2018 Integrated Device Technology, Inc.

6

October 24, 2018

Pin Descriptions

Table 1.

Pin Descriptions

Number

Name

Description

1

RFIN_A

Input RF port for channel A which is internally matched to 50Ω. Must use external DC block.

2, 8, 15, 16,

17, 29, 30, 31

GND

Internally grounded. This pin must be grounded with a via as close to the pin as possible.

3

VCTRL0_A

1-bit DSA0 6dB attenuator control for channel A. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB

attenuated.

4

DATA

Data input: 3.3V or 1.8V CMOS compatible.

5

CLK

Clock input: 3.3V or 1.8V CMOS compatible.

6, 21, 23, 25

Power Supply. Use bypass capacitors as close to pin as possible.

7

VCTRL0_B

1-bit DSA0 6dB attenuator control for channel B. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB

attenuated.

9

RFIN_B

Input RF port for channel B that is internally matched to 50Ω. Must use external DC block.

10, 18, 20, 26,

28, 36

NC

No internal connection. These pins can be left unconnected or be connected to ground (recommended). Use a via as

close to the pin as possible if grounded.

11

CSb_B

Chip Select bar input for channel B: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.

12

STBY_B

Standby pin for channel B (LOW/Open = device power ON, HIGH = device power OFF with SPI still powered ON). An

internal pull-down resistor of 57kΩ connects between this pin and GND.

13

VCTRL1_B

Bit 0 for DSA2 channel B attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.

14

VCTRL2_B

Bit 1 for DSA2 channel B attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated.

19

RFOUT_B

Output RF port for channel B. Use external DC block as close to the pin as possible.

22

RDSET

Connect external resistor to GND to optimize amplifier bias. Used with pin 24.

24

RSET

Connect external resistor to GND to optimize amplifier bias. Used with pin 22.

27

RFOUT_A

Output RF port for channel A. Use external DC block as close to the pin as possible.

32

VCTRL2_A

Bit 1 for DSA2 channel A attenuator. Logic HIGH is for 12dB attenuated and logic LOW is for 0dB attenuated.

33

VCTRL1_A

Bit 0 for DSA2 channel A attenuator. Logic HIGH is for 6dB attenuated and logic LOW is for 0dB attenuated.

34

STBY_A

Standby pin for channel A (LOW/Open = device power ON, HIGH = device power OFF with SPI still powered ON). An

internal pull-down resistor of 57kΩ connects between this pin and GND.

35

CSb_A

Chip Select bar input for channel A: 3.3V or 1.8V CMOS compatible. Logic LOW allows data to be shifted in.

— EPAD

Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB) pad that

uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple ground

vias are also required to achieve the specified RF performance.