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F0448 Datasheet(PDF) 8 Page - Renesas Technology Corp

Part # F0448
Description  Dual Matched Broadband RF DVGA 3.4GHz to 3.8GHz
PDF  35 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

F0448 Datasheet(HTML) 8 Page - Renesas Technology Corp

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F0448 Datasheet
© 2018 Integrated Device Technology, Inc.
8
October 24, 2018
Electrical Characteristics
See F0448 Typical Application Circuit. VCC = +5V, TC = +25°C, fRF = 3.6GHz specifications apply when operated as a dual-channel RF DVGA,
maximum gain setting, POUT = 0dBm, ZRFI = ZRFO = 50Ω, Evaluation Board (EVKit) traces and connectors are de-embedded, unless otherwise
stated.
Table 4.
Electrical Characteristics
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Logic Input High
VIH
Applies for all logic levels.
1.07 [a]
V
Logic Input Low
VIL
Applies for all logic levels.
0.63
V
Logic Current
(CLK, DATA, CSb_A, CSb_B,
VCTRL0_A, VCTRL1_A, VCTRL2_A,
VCTRL0_B, VCTRL1_B, VCTRL2_B)
IIH, IIL
-5
5
μA
Logic Current for Standby
(STBY_A, STBY_B) [b]
IIH-SB, IIL-SB
5V logic
-5
127
μA
3.3V logic
-5
87
1.8V logic
-5
47
Supply Current
ICC_2
Both channels on
220
270
mA
ICC_1
One channel on
110
142
ICC_STBY
Standby Mode
7
14
Startup Time
tSTART
50% of STBY going LOW to Gain
within ± 1dB with no attenuation.
74
ns
DSA0 Adjustment Range
AADJ0
6dB step size
6
dB
DSA1 Adjustment Range
AADJ1
1dB step size
23
dB
DSA2 Adjustment Range
AADJ2
6dB step size
18
dB
Maximum Attenuation Glitch
ATTNG
2
dB
DSA0 Gain Settling Time
tDSA0_1
50% CTRL to within 0.1dB final value,
0dB state to 6dB state
24
35
ns
tDSA0_2
50% CTRL to within 0.1dB final value,
6dB state to 0dB state
18
35
DSA1 Gain Settling Time
tDSA1
50% of CSb to within 0.1dB final value
300
ns
DSA2 Gain Settling Time
tDSA2_1
50% CTRL to within 0.1dB final value,
0dB state to 18dB state
16
35
ns
tDSA2_2
50% CTRL to within 0.1dB final value,
18dB state to 0dB state
15
35
DSA0 Phase Settling Time
tDSA0_1_PH 50% CTRL to within 1 degree of final
value, 0dB state to 6dB state
24
35
ns
tDSA0_2_PH 50% CTRL to within 1 degree of final
value, 6dB state to 0dB state
18
35



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