LT3755 datasheet(17/32 Pages) AD

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LT8393

Rev. A

For more information www.analog.com

Shutdown and Power-On-Reset

The LT8393 enters shutdown mode and drains less than

2µA quiescent current when the EN/UVLO pin is below its

shutdown threshold (0.3V minimum). Once the EN/UVLO

pin is above its shutdown threshold (1V maximum), the

LT8393 wakes up startup circuitry, generates bandgap

reference, and powers up the internal INTVCC LDO. The

INTVCC LDO supplies the internal control circuitry and

gate drivers. Now the LT8393 enters undervoltage lockout

(UVLO) mode with a hysteresis current (2.5µA typical)

pulled into the EN/UVLO pin. When the INTVCC pin is

charged above its rising UVLO threshold (3.78V typi-

cal), the EN/UVLO pin passes its rising enable threshold

(1.233V typical), and the junction temperature is less than

its thermal shutdown (165°C typical), the LT8393 enters

enable mode, in which the EN/UVLO hysteresis current is

turned off and the voltage reference VREF is being charged

up from ground. From the time entering enable mode to

the time VREF passes its rising UVLO threshold (1.89V

typical),theLT8393goesthroughapower-on-reset(POR),

waking up the entire internal control circuitry and settling

to the right initial conditions. After the POR, the LT8393 is

ready and waiting for the signals on the CTRL and PWM

pins to start switching.

Start-Up and Fault Protection

Figure 8 shows the start-up and fault sequence for the

LT8393. During the POR state, the SS pin is hard pulled

down with a 100Ω to ground. In a pre-biased condition,

the SS pin has to be pulled below 0.2V to enter the INIT

state, where the LT8393 wait 10µs so that the SS pin can

be fully discharged to ground. After the 10µs, the LT8393

enters the UP/PRE state when the PWMON signal goes

high. The PWMON high signal happens when CTRL pin

is above its rising dim-off threshold (0.228V typical) and

the external or internal PWM dimming is on.

During the UP/PRE state, the SS pin is charged up by a

12.5µA pull-up current while the switching is disabled

and the PMWTG is turned off. Once the SS pin is charged

above 0.25V, the LT8393 enters the UP/TRY state, where

the PMWTG is turned on first while the switching is still

disabled. This is to check for an output overvoltage con-

dition for the LED string before delivering any switching

energy. In the case of a higher voltage output capacitor

connected to a lower voltage LED string, the excessive

current flowing through the LED string and current sense

resistortriggerstheISP/ISNovercurrent(ISOC)signaland

resets the LT8393 back into the POR state. The LT8393

will hiccup with SS pin between 0V and 0.25V and bypass

the POR, INIT, UP/PRE, and UP/TRY states to slowly

discharge the voltage output capacitor until its voltage

gets closer to the lower voltage LED string. After 10µs in

the UP/TRY state without triggering the ISOC signal, the

LT8393 enters the UP/RUN state.

Figure 8. Start-Up and Fault Sequence

INIT

SS < 0.2V

• SS HARD PULL DOWN

• SWITCHING DISABLED

• PWMTG TURNED OFF

• NO OPEN/SHORT DETECTION

WAIT 10µs AND

PWMON = HI

WAIT 10µs

POR = HI OR

ISOC = HI

OPEN LED OR

SHORT LED

8393 TA08

SS < 0.2V AND

PWMON = HI

SS > 0.25V

SS > 1.75V

SS < 1.7V

UP/PRE

• SS 12.5µA PULL UP

• SWITCHING DISABLED

• PWMTG TURNED OFF

• NO OPEN/SHORT DETECTION

OK/RUN

• SS 12.5µA PULL UP

• SWITCHING ENABLED

• PWMTG TURNED ON

• OPEN/SHORT DETECTION

FAULT/RUN

• SS 1.25µA PULL DOWN

• SWITCHING ENABLED

• PWMTG TURNED ON

• OPEN/SHORT DETECTION

POR

• SS HARD PULL DOWN

• SWITCHING DISABLED

• PWMTG TURNED OFF

• NO OPEN/SHORT DETECTION

UP/TRY

• SS 12.5µA PULL UP

• SWITCHING DISABLED

• PWMTG TURNED ON

• NO OPEN/SHORT DETECTION

UP/RUN

• SS 12.5µA PULL UP

• SWITCHING ENABLED

• PWMTG TURNED ON

• NO OPEN/SHORT DETECTION

DOWN/STOP

• SS 1.25µA PULL DOWN

• SWITCHING DISABLED

• PWMTG TURNED ON

• NO OPEN/SHORT DETECTION

OPERATION

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