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PCI1520PDVG4 Datasheet(PDF) 26 Page - Texas Instruments |
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PCI1520PDVG4 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 140 page  2−13 Table 2−8. PCI Address and Data Terminals TERMINAL NAME NO. I/O DESCRIPTION NAME PDV GHK I/O DESCRIPTION AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 171 172 175 176 178 179 167 181 184 186 187 188 189 190 191 192 205 206 207 208 173 1 2 3 5 7 8 9 10 11 12 13 E12 C12 A11 B11 E11 F11 F12 B10 F10 B09 C09 F09 E09 A08 B08 C08 B05 E06 C05 A04 B12 D01 E03 F05 E02 F03 F02 G05 F01 H06 G03 G02 I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a 32-bit address or other destination information. During the data phase, AD31−AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 164 193 204 4 B14 F08 F06 G06 I/O PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary-bus PCI cycle, C/BE3−C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8), C/BE2 applies to byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24). PAR 203 A05 I/O PCI-bus parity. In all PCI-bus read and write cycles, the PCI1520 calculates even parity across the AD31−AD0 and C/BE3−C/BE0 buses. As an initiator during PCI cycles, the PCI1520 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the PCI1520 compares its calculated parity to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR). |
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