© VITESSE SEMICONDUCTOR CORPORATION

Page 11

10/12/98

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8150

2.488Gb/s SONET/SDH

Overhead Monitor

G52186-0, Rev. 3.0

Table 8: Framing and B1 Error Output Timing (STS-3/STM-1 Mode)

Note: Generated Waveforms are synchronous and assume a 155MHz RXSCLKIN signal.

Figure 11: Serial Data Input Timing Diagram

Table 9: Serial Data Input Timing

Parameter

Description

Min

Typ

Max

Units

Frame Pulse Width

—

51.4

—

ns

Frame Boundary Error delay with respect to RXFPOUT

—

0

—

ns

Frame Boundary Error pulse width high

—

51.4

—

ns

SEF transition delay time with respect to RXFPOUT

—

103

—

ns

B1 Pulse train delay with respect to RXFPOUT

—

13.96

—

µs

B1 error pulse width high

—

409

—

ns

B1 error pulse width low

—

409

—

ns

Parameter

Description

Min

Typ

Max

Units

Serial Receive clock period

401.9

-

-

ps

Serial Receive input data RXSIN setup time with respect

to falling edge of RXSCLKIN+

100

-

-

ps

Serial Receive input data RXSIN hold time with respect

to falling edge of RXSCLKIN+

75

-

-

ps

Propagation delay from falling edge of RXSCLKIN+

430

-

820

ps

RXSCLKIN-

RXSCLKIN+

RXSIN+

RXSIN-

RXSLBOUT+

RXSLBOUT-