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ATMEGA640 Datasheet(PDF) 228 Page - Microchip Technology |
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ATMEGA640 Datasheet(HTML) 228 Page - Microchip Technology |
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228 / 436 page ![]() 228 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A correctly. Preferably the DDR_XCKn should be set up before the USART in MSPIM is enabled (that is, TXENn and RXENn bit set to one). The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 23-1. Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps). BAUD Baud rate (in bits per second, bps). fOSC System Oscillator clock frequency. UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095). 23.3 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 23-1. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabi- lize. The UCPOLn and UCPHAn functionality is summarized in Table 23-2. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. Figure 23-1. UCPHAn and UCPOLn data transfer timing diagrams. Table 23-1. Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRRn Value Synchronous Master mode BAUD fOSC 2 UBRRn 1 + --------------------------------------- = UBRRn fOSC 2BAUD -------------------- 1 – = Table 23-2. UCPOLn and UCPHAn Functionality. UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge 0 0 0 Sample (Rising) Setup (Falling) 0 1 1 Setup (Rising) Sample (Falling) 1 0 2 Sample (Falling) Setup (Rising) 1 1 3 Setup (Falling) Sample (Rising) XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) UCPOL=0 UCPOL=1 |
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