ATMEGA640 datasheet(69/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

13.2.3

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an inter-

mediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must

occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the

difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register

can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-

state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

13.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As

shown in Figure 13-2 on page 68, the PINxn Register bit and the preceding latch constitute a synchronizer. This is

needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also intro-

duces a delay. Figure 13-3 on page 69 shows a timing diagram of the synchronization when reading an externally

applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.

Figure 13-3. Synchronization when Reading an Externally Applied Pin value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when

the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC

Table 13-1.

Port Pin Configurations

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled low

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

XXX

in r17, PINx

0x00

0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

t pd, min

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