ATMEGA640 datasheet(277/436 Pages) MICROCHIP

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277

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

Figure 26-10. ADC Power Connections, ATmega640/1280/2560

26.6.3

Offset Compensation Schemes

The stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as

possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both

differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this

kind of software based offset correction, offset on any channel can be reduced below one LSB.

26.6.4

ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2

n steps (LSBs). The lowest code

is read as 0, and the highest code is read as 2n-1.

Several parameters describe the deviation from the ideal behavior:

•

Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal

value: 0 LSB.

100nF

Ground Plane

100

μΗ

PJ7

VCC

GND

(ADC15/PCINT23) PK7

(ADC14/PCINT22) PK6

(ADC13/PCINT21) PK5

(ADC12/PCINT20) PK4

(ADC11/PCINT19) PK3

(ADC10/PCINT18) PK2

(ADC9/PCINT17) PK1

(ADC8/PCINT16) PK0

(ADC7/TDI) PF7

(ADC6/TDO) PF6

(ADC5/TMS) PF5

(ADC4/TCK) PF4

(ADC3) PF3

(ADC2) PF2

(ADC1) PF1

(ADC0) PF0

AREF

GND

AVCC

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