ATMEGA640 datasheet(298/436 Pages) MICROCHIP

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298

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

28.4.3

SAMPLE_PRELOAD; 0x2

Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins with-

out affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan

Chain is selected as Data Register.

The active states are:

•

Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain

•

Shift-DR: The Boundary-scan Chain is shifted by the TCK input

•

Update-DR: Data from the Boundary-scan chain is applied to the output latches. However, the output latches

are not connected to the pins

28.4.4

AVR_RESET; 0xC

The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG

reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data

chain is not latched.

The active states are:

•

Shift-DR: The Reset Register is shifted by the TCK input

28.4.5

BYPASS; 0xF

Mandatory JTAG instruction selecting the Bypass Register for Data Register.

The active states are:

•

Capture-DR: Loads a logic “0” into the Bypass Register

•

Shift-DR: The Bypass Register cell between TDI and TDO is shifted

28.5 Boundary-scan Chain

The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well

as the boundary between digital and analog logic for analog circuitry having off-chip connection.

28.5.1

Scanning the Digital Port Pins

Figure 28-3 on page 299 shows the Boundary-scan Cell for a bi-directional port pin. The pull-up function is disabled

during Boundary-scan when the JTAG IC contains EXTEST or SAMPLE_PRELOAD. The cell consists of a bi-

directional pin cell that combines the three signals Output Control - OCxn, Output Data - ODxn, and Input Data -

IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the following description.

The Boundary-scan logic is not included in the figures in the datasheet. Figure 28-4 on page 300 shows a simple

digital port pin as described in the section “I/O-Ports” on page 67. The Boundary-scan details from Figure 28-3 on

page 299 replaces the dashed box in Figure 28-4 on page 300.

When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Register value (but ID

has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data

Direction - DD Register, and the Pull-up Enable - PUExn - corresponds to logic expression PUD · DDxn · PORTxn.

Digital alternate port functions are connected outside the dotted box in Figure 28-4 on page 300 to make the scan

chain read the actual pin value. For analog function, there is a direct connection from the external pin to the analog

circuit. There is no scan chain on the interface between the digital and the analog circuitry, but some digital control

signal to analog circuitry are turned off to avoid driving contention on the pads.

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