ATMEGA640 datasheet(109/436 Pages) MICROCHIP

109 / 436 page

109

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

15. External Interrupts

The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23:0 pins. Observe that, if enabled, the

interrupts will trigger even if the INT7:0 or PCINT23:0 pins are configured as outputs. This feature provides a way

of generating a software interrupt.

The Pin change interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change interrupt PCI1 if any

enabled PCINT15:8 toggles and Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles.

PCMSK2, PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change

interrupts on PCINT23:0 are detected asynchronously. This implies that these interrupts can be used for waking

the part also from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the

specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4). When the external

interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low.

Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-

rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all

sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long

enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of

the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the

SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 39.

15.1 Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 15-1.

Figure 15-1. Normal pin change interrupt.

clk

PCINT(n)

pin_lat

pin_sync

pcint_in_(n)

pcint_syn

pcint_setflag

PCIF

PCINT(0)

pin_sync

pcint_syn

pin_lat

pcint_setflag

PCIF

clk

PCINT(0) in PCMSK(x)

pcint_in_(0)

ATMEGA640 Datasheet(PDF) 109 Page - Microchip Technology

ATMEGA640 Datasheet(HTML) 109 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL