ATMEGA640 datasheet(131/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

16.9.6

TIMSK0 – Timer/Counter Interrupt Mask Register

• Bits 7:3, 0 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare

Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs,

that is, when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare

Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0

occurs, that is, when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow inter-

rupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the

TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.

16.9.7

TIFR0 – Timer/Counter 0 Interrupt Flag Register

• Bits 7:3, 0 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output

Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter

Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Out-

put Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling

vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A

(Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Inter-

rupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the

Bit

7654

(0x6E)

––––

–

OCIE0B

OCIE0A

TOIE0

TIMSK0

Read/Write

R/W

Initial Value

0000

Bit

76543

210

0x15 (0x35)

–––––

OCF0B

OCF0A

TOV0

TIFR0

Read/Write

RRRRR

R/W

Initial Value

00000

000

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