OPA615 datasheet(20/26 Pages) TI

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Fast Pulse Peak Detector

+2.5

+1.5

+0.5

−0.5

−1.5

−2.5

1MHz SAMPLE−AND− HOLD OF A 100kHz SINEWAVE

Time (1

µs/div)

Hold Control

OUT

Ω

100

Ω

150

Ω

100

Ω

100

Ω

OTA

−V

OUT

300

Ω

27pF

BUF602

OPA615

SOTA

Phase Detector for Fast PLL Systems

Integrator for ns-Pulses

150

Ω

Hold Control

27pF

100

Ω

820

Ω

µF

620

Ω

O T A

OUT

SOTA

R EF

IN T

+5V

O UT

R EF

O UT

O UT = fRE F x N

OU T

R EF

OU T

Ω

√N

Phase

VCO

OTA

OPA615

Ω

100

Ω

OPA615

SBOS299B – FEBRUARY 2004 – REVISED JULY 2005

To illustrate how the digitization is realized in the

Figure 45 circuit, Figure 46 shows a 100kHz

A circuit similar to that shown in Figure 47 (the

sinewave being sampled at a rate of 1MHz. The

integrator for ns-pulses) can be devised to detect and

output signal used here is the I

OUT output driving a

isolate positive pulses from negative pulses. This

Ω load.

circuit, shown in Figure 48, uses the OPA615 as well

as the BUF602. This circuit makes use of diodes to

isolate the positive-going pulses from the nega-

tive-going pulses and charge-different capacitors.

Figure 46. 1MHz Sample-and-Hold of a 100kHz

Figure 48. Fast Bipolar Peak Detector

Sine Wave

Figure 49 shows the circuit for a phase detector for

The integrator for ns-pulses using the OPA615

fast PLL systems. Given a reference pulse train fREF

(shown in Figure 47) makes use of the fast

and a pulse train input signal fIN out of phase, the

comparator and its current-mode output. Placing the

SOTA of the OPA615 acts in this circuit as a

hold-control high, a narrow pulse charges the capaci-

comparator, either charging or discharging the ca-

tor, increasing the average output

voltage.

pacitor. This voltage is then buffered by the OTA and

minimize ripples at the inverting input and maximize

fed to the VCO.

the capacitor charge, a T-network is used in the

feedback path.

Figure 47. Integrator for ns-Pulses

Figure 49. Phase Detector For Fast PLL-Systems

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