LTC7803 datasheet(34/42 Pages) AD

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LTC7811

Rev. 0

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5. Losses in the boost channel output diode. The power

dissipation in the diode is :

PDIODE = IOUT3(MAX) • VF

This diode can be a significant contributor to power

loss. For an 8V output with 7A of load current, a

Schottky diode with a 0.4V voltage drop dissipates

2.8W, which equates to a 5% power loss.

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

losses can be minimized by making sure that CIN has ade-

quate charge storage and very low ESR at the switching

frequency. A 25W supply will typically require a minimum

of 20μF to 40μF of capacitance having a maximum of

20mΩ to 50mΩ of ESR. The LTC7811 2-phase architec-

ture typically halves this input capacitance requirement

over competing solutions. Other losses including induc-

tor core losses generally account for less than 2% total

additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to ΔILOAD • (ESR), where ESR is the effective

series resistance of COUT. ΔILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capaci-

tance and ESR values. The availability of the ITH pin not

only allows optimization of control loop behavior, but it

also provides a DC coupled and AC filtered closed loop

response test point. The DC step, rise time and settling

at this test point truly reflects the closed loop response.

Assuming a predominantly second order system, phase

APPLICATIONS INFORMATION

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin. The bandwidth

can also be estimated by examining the rise time at the

pin. The ITH external components shown in the Typical

Applications circuits provide an adequate starting point

for most applications.

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their initial values) to optimize tran-

sient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

Placing a power MOSFET directly across the output

capacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better to

look at the ITH pin signal which is in the feedback loop and

is the filtered and compensated control loop response.

The gain of the loop will be increased by increasing RC and

the bandwidth of the loop will be increased by decreas-

ing CC. If RC is increased by the same factor that CC is

decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual over-

all supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

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