LTC7803 datasheet(16/42 Pages) AD

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LTC7811

Rev. 0

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OPERATION

number of cycles (i.e., skipping pulses). The inductor cur-

rent is not allowed to reverse (discontinuous operation).

This mode, like forced continuous operation, exhibits low

output ripple as well as low audio noise and reduced RF

interference as compared to Burst Mode operation. It pro-

vides higher low current efficiency than forced continuous

mode, but not nearly as high as Burst Mode operation.

Unlike forced continuous mode and pulse-skipping mode,

Burst Mode cannot be synchronized to an external clock.

Therefore, if Burst Mode is selected and the switching

frequency is synchronized to an external clock applied to

the PLLIN/SPREAD pin, the LTC7811 switches from Burst

Mode to forced continuous mode.

Frequency Selection, Spread Spectrum, and Phase-

Locked Loop (FREQ and PLLIN/SPREAD Pins)

The free running switching frequency of the LTC7811

controllers is selected using the FREQ pin. Tying FREQ to

GND selects 380kHz while tying FREQ to INTVCC selects

2.25MHz. Placing a resistor between FREQ and GND

allows the frequency to be programmed between 100kHz

and 3MHz.

Switching regulators can be particularly troublesome for

applications where electromagnetic interference (EMI) is

a concern. To improve EMI, the LTC7811 can operate in

spread spectrum mode, which is enabled by tying the

PLLIN/SPREAD pin to INTVCC. This feature varies the

switching frequency within typical boundaries of −12%

to ±15% of the frequency set by the FREQ pin.

A phase-locked loop (PLL) is available on the LTC7811

to synchronize the internal oscillator to an external

clock source connected to the PLLIN/SPREAD pin. The

LTC7811’s PLL aligns the turn-on of controller 1’s exter-

nal top MOSFET to the rising edge of the synchronizing

signal. Thus, the turn-on of controller 2’s external top

MOSFET is 180° out-of-phase to the rising edge of the

external clock source.

The PLL frequency is prebiased to the free running fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL only needs to make slight changes in order to

synchronize the rising edge of the external clock to the

rising edge of TG1. For more rapid lock-in to the external

clock, use the FREQ pin to set the internal oscillator to

approximately the frequency of the external clock. The

LTC7811’s PLL is guaranteed to lock to an external clock

source whose frequency is between 100kHz and 3MHz.

The PLLIN/SPREAD pin is TTL compatible with thresholds

of 1.6V (rising) and 1.1V (falling) and is guaranteed to

operate with a clock signal swing of 0.5V to 2.5V.

Boost Controller at Low Input Voltage

The LTC7811 features a rail-to-rail current comparator for

the boost channel which functions down to zero volts. The

minimum boost converter input voltage is therefore deter-

mined by the practical limitations of the boost converter

architecture. Since the input voltage could be lower than

the 4.5V VBIAS limit, VBIAS can be connected to the output

of the boost controller, as illustrated in the typical applica-

tion circuit in Figure 10. This allows the boost controller to

handle very low input voltage transients while maintaining

output voltage regulation.

Buck Controller Output Overvoltage Protection

The two buck channels have an overvoltage comparator

that guards against transient overshoots as well as other

more serious conditions that may overvoltage their out-

puts. When the VFB1,2 pin rises more than 10% above its

regulation point of 0.8V, the top MOSFET is turned off and

the bottom MOSFET is turned on until the overvoltage

condition is cleared.

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