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TAS6424-Q1 Datasheet(PDF) 44 Page - Texas Instruments |
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TAS6424-Q1 Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 77 page ![]() 9.6.6 Channel 1 Through 4 Volume Control Registers (address = 0x05–0x08) [default = 0xCF] The Channel 1 Through 4 Volume Control registers are shown in Figure 9-18 and described in Table 9-15. Figure 9-18. Channel x Volume Control Register 7 6 5 4 3 2 1 0 CH x VOLUME R/W-CF Table 9-15. Ch x Volume Control Field Descriptions Bit Field Type Reset Description 7–0 CH x VOLUME R/W 0xCF 8-Bit Volume Control for each channel, register address for Ch1 is 0x05, Ch2 is 0x06, Ch3 is 0x07 and Ch4 is 0x08, 0.5 dB/step: 0xFF: 24 dB 0xCF: 0 dB 0x07: –100 dB < 0x07: MUTE 9.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00] The DC Diagnostic Control 1 register is shown in Figure 9-19 and described in Table 9-16. Figure 9-19. DC Load Diagnostic Control 1 Register 7 6 5 4 3 2 1 0 DC LDG ABORT 2x_RAMP 2x_SETTLE RESERVED LDG LO ENABLE LDG BYPASS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 9-16. DC Load Diagnostics Control 1 Field Descriptions Bit Field Type Reset Description 7 DC LDG ABORT R/W 0 0: Default state, clear after abort 1: Aborts the load diagnostics in progress 6 2x_RAMP R/W 0 0: Normal ramp time 1: Double ramp time 5 2x_SETTLE R/W 0 0: Normal Settle time 1: Double settling time 4–2 RESERVED R/W 000 RESERVED 1 LDG LO ENABLE R/W 0 0: Line output diagnostics are disabled 1: Line output diagnostics are enabled 0 LDG BYPASS R/W 0 0: Automatic diagnostics when leaving Hi-Z and after channel fault 1: Diagnostics are not run automatically TAS6424E-Q1 SLOSE73 – JUNE 2021 www.ti.com 44 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TAS6424E-Q1 |
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