REV. C

–14–

AD8316

shunted by a second capacitor and resistor in series will also be

useful in minimizing the settling time of the loop.

Mobile Handset Power Control Example

Figure 8 shows a complete power amplifier control circuit for a

dual-mode handset. The RF3108 (RF Micro Devices), dual-

input, trimode (GSM, DCS, PCS) PA is driven by a nominal

power level of 6 dBm at both inputs and has two gain control

lines. Some of the output power from the PA is coupled off

using a dual-band directional coupler (Murata part number

LDC15D190A0007A). This has a coupling factor of approxi-

mately 20 dB for the GSM band and 15 dB for DCS and an

insertion loss of 0.38 dB and 0.45 dB, respectively. Because the

RF3108 transmits a maximum power level of approximately

35 dBm for GSM and 32 dBm for DCS/PCS, additional attenua-

tion of 20 dB is required before the coupled signal is applied to

the AD8316. This results in peak input levels of –5 dBm (GSM)

and –3 dBm (DCS). While the AD8316 gives a linear response

for input levels up to +3 dBm, for highly temperature-stable

performance at maximum PA output power, the maximum

input level should be limited to approximately –3 dBm (see

TPC 3 and TPC 5). This does, however, reduce the sensitivity

of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V,

is applied to the VSET pin of the AD8316. This will typically be

supplied by a DAC. The desired output is selected by applying

a high or low signal to the BSEL pin (HI = OUT1, LO = OUT2).

The selected output directly drives the level control pin of the

power amplifier. In this case a minimum supply voltage of 2.9 V

low power supply to the AD8316 can be used. For example, on

a 2.7 V supply, the voltage on OUT1/OUT2 can come to within

approximately 100 mV of the supply rail. This will depend, how-

ever, on the current draw (see TPC 19).

During initialization and completion of the transmit sequence,

DAC that has an output range from 0 V to 2.55 V or 10 mV

(0.04 dB/mV

10 mV). If finer resolution is required, the

DAC’s output voltage can be scaled using two resistors as

shown. This converts the DAC’s maximum voltage of 2.55 V

down to 1.6 V and increases the control resolution to 0.25 dB/bit.

large degree on the gain control dynamics of the power ampli-

fier, something that is frequently poorly characterized, so some

trial and error may be necessary. In this example, a 220 pF

capacitor is used. The user may want to add a resistor in series

with the filter capacitor. The resistor adds a zero to the control

loop and increases the phase margin, which helps to make the

step response of the circuit more stable when the slope of the

PA’s power control function is the steepest. In this example,

the two filter capacitors are equal values; however, this is not

a requirement.

A smaller filter capacitor can be used by inserting a series resis-

resistor will work with the input impedance of the PA to create a

resistor divider and will reduce the loop gain. The size of the

resistor divider ratio depends upon the available output swing of

nique can also be used to limit the control voltage in situations

drive of the control input of some PAs causes increased distortion.

RF3108

4.7 F

1 F

3.5V

GSM RF IN

+6dBm

DCS/PCS RF IN

+6dBm

GND

R6

(R5, R6 OPTIONAL)

(SEE TEXT)

8-BIT

RAMP DAC

0V 2.55V

R2

600

R3

1k

ENABLE

R4

576

AD8316

OUT2

VPOS

OUT1

COMM

FLT1

RFIN

ENBL

VSET

1

2

3

4

10

9

8

7

FLT2

BSEL

56

220pF

2.7V TO 5.5V

C1

0.1 F

R5

54.9

R1

52.3

GSM/DCS

16.5dBm/19dBm

220pF

BAND SELECT

GSM/(DCS/PCS)

(R2, R3 OPTIONAL)

(SEE TEXT)

5

2

6

3

4

8

LDC15D190A0007A

R7

49.9

7

1

GSM

RF OUTPUT

+35.5dBm MAX

TO

T/R SWITCH

21.5dB ATTENUATOR

PCS/DCS

RF OUTPUT

+33dBm MAX

R8

Figure 8. Dual-Mode (GSM/DCS) PA Control Example (Shown with AD8316 MSOP Pinout)