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MCP47FVB21 Datasheet(PDF) 32 Page - Microchip Technology |
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MCP47FVB21 Datasheet(HTML) 32 Page - Microchip Technology |
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32 / 92 page  MCP48FEBXX DS20005429B-page 32 2015 Microchip Technology Inc. 4.2.3 DEVICE CONFIGURATION MEMORY There are up to five nonvolatile user bits that are not directly mapped into the address space. These nonvolatile device configuration bits control the following functions: •DAC Register • Configuration WiperLock Technology (2 bits per DAC) The Status register shows the states of the device WiperLock Technology configuration bits. The Status register is described in Register 4-6. The operation of WiperLock Technology is discussed in Section 4.2.6 “WiperLock Technology”. 4.2.4 UNIMPLEMENTED REGISTER BITS Read commands of a valid location will read unimplemented bits as ‘0’. 4.2.5 UNIMPLEMENTED (RESERVED) LOCATIONS Normal (voltage) commands (read or write) to any unimplemented memory address (reserved) will result in a command error condition (CMDERR). Read commands of a reserved location will read bits as ‘1’. High-Voltage commands (enable or disable) to any unimplemented configuration bits will result in a command error condition (CMDERR). 4.2.5.1 Default Factory POR Memory State of Nonvolatile Memory (EEPROM) Table 4-2 shows the default factory POR initialization of the device memory map for the 8-, 10- and 12-bit devices. Note: The volatile memory locations will be determined by the nonvolatile memory states (registers and device configuration bits). TABLE 4-2: FACTORY DEFAULT POR / BOR VALUES Function POR/BOR Value Function POR/BOR Value 00h Volatile DAC0 Register 7Fh 1FFh 7FFh 10h Nonvolatile DAC0 Register 7Fh 1FFh 7FFh 01h Volatile DAC1 Register 7Fh 1FFh 7FFh 11h Nonvolatile DAC1 Register 7Fh 1FFh 7FFh 02h Reserved (1) FFh 3FFh FFFh 12h Reserved (1) FFh 3FFh FFFh 03h Reserved (1) FFh 3FFh FFFh 13h Reserved (1) FFh 3FFh FFFh 04h Reserved (1) FFh 3FFh FFFh 14h Reserved (1) FFh 3FFh FFFh 05h Reserved (1) FFh 3FFh FFFh 15h Reserved (1) FFh 3FFh FFFh 06h Reserved (1) FFh 3FFh FFFh 16h Reserved (1) FFh 3FFh FFFh 07h Reserved (1) FFh 3FFh FFFh 17h Reserved (1) FFh 3FFh FFFh 08h VREF Register 0000h 0000h 0000h 18h Nonvolatile VREF Register 0000h 0000h 0000h 09h Power-Down Register 0000h 0000h 0000h 19h Nonvolatile Power-Down Register 0000h 0000h 0000h 0Ah Gain and Status Register 0080h 0080h 0080h 1Ah NV Gain 0000h 0000h 0000h 0Bh WiperLock™ Technology Status Register 0000h 0000h 0000h 1Bh Reserved (1) FFh 3FFh FFFh 0Ch Reserved (1) FFh 3FFh FFFh 1Ch Reserved (1) FFh 3FFh FFFh 0Dh Reserved (1) FFh 3FFh FFFh 1Dh Reserved (1) FFh 3FFh FFFh 0Eh Reserved (1) FFh 3FFh FFFh 1Eh Reserved (1) FFh 3FFh FFFh 0Fh Reserved (1) FFh 3FFh FFFh 1Fh Reserved (1) FFh 3FFh FFFh Volatile Memory address range Nonvolatile Memory address range Note 1: Reading a reserved memory location will result in the SPI command Command Error condition. The SDO pin will output all ‘0’s. Forcing the CS pin to the VIH state will reset the SPI interface. |
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