MCP47FVB21 datasheet(54/92 Pages) MICROCHIP

54 / 92 page

MCP48FEBXX

DS20005429B-page 54

 2015 Microchip Technology Inc.

6.5

Interface Pins (CS, SCK, SDI, SDO,

and LAT/HVC)

The operation of the five interface pins and the

High Voltage command (HVC) pin are discussed in

this section. These pins are:

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock)

•CS (Chip Select)

•LAT/HVC (High Voltage command)

The serial interface works on either 8-bit or 24-bit

boundaries depending on the selected command. The

Chip Select (CS) pin frames the SPI commands.

6.5.1

SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal into

the device. The value on this pin is latched on the

rising edge of the SCK signal.

6.5.1.1

Serial Data Out (SDO)

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

Once the CS pin is forced to the active level (VIL or

VIHH), the SDO pin will be driven. The state of the

SDO pin is determined by the serial bit’s position in the

command, the command selected, and if there is a

command error state (CMDERR).

6.5.1.2

Serial Clock (SCK)

(SPI Frequency Of Operation)

The SPI interface is specified to operate up to 20 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

TABLE 6-1:

SCK FREQUENCY

6.5.1.3

The CS Signal

The Chip Select (CS) signal is used to select the

device and frame a command sequence. To start a

command, or sequence of commands, the CS signal

must transition from the inactive state (VIH) to an

active state (VIL or VIHH).

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

If an error condition occurs for an SPI command, then

the Command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (VIL). To exit the

error condition, the user must take the CS pin to the

VIH level.

When the CS pin returns to the inactive state (VIH), the

SPI module resets (including the address pointer).

While the CS pin is in the inactive state (VIH), the serial

interface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,

SDO, and SCK signals.

6.5.1.4

The HVC Signal

The high-voltage capability of the HVC pin allows High

Voltage commands. High Voltage commands allow the

device’s WiperLock Technology and write protect

features to be enabled and disabled.

6.5.2

THE SPI MODES

The SPI module supports two (of the four) standard

SPI modes. These are Mode 0,0 and 1,1. The mode

is determined by the state of the SDI pin on the rising

edge of the 1st clock bit (of the 8-bit byte).

6.5.2.1

Mode 0,0

In Mode 0,0:

• SCK idle state = low (VIL)

• Data is clocked in on the SDI pin on the rising

edge of SCK

• Data is clocked out on the SDO pin on the falling

edge of SCK

6.5.2.2

Mode 1,1

In Mode 1,1:

• SCK idle state = high (VIH)

• Data is clocked in on the SDI pin on the rising

edge of SCK

• Data is clocked out on the SDO pin on the falling

edge of SCK

Memory Type Access

Command

Read

Write,

Enable,

Disable

Nonvolatile

Memory

SDI, SDO

10 MHz 20 MHz (1, 2)

Volatile

Memory

SDI, SDO

10 MHz

20 MHz (2)

Note 1:

After a write command, the internal write

cycle must complete before the next SPI

command is received.

This is a design goal. The SDO pin

performance is believed to be the limiting

factor.

Note:

There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

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