MCP47FVB21 datasheet(51/92 Pages) MICROCHIP

51 / 92 page

 2015 Microchip Technology Inc.

DS20005429B-page 51

MCP48FEBXX

5.6.1

EXITING POWER-DOWN

When the device exits Power-Down mode, the

following occurs:

• Disabled circuits (op amp, resistor ladder, et al.)

are turned on

• The resistor ladder is connected to selected

reference voltage (VRL)

• The selected pull-down resistor is disconnected

•The VOUT output will be driven to the voltage

represented by the volatile DAC Register’s value

and configuration bits

The VOUT output signal will require time as these

circuits are powered-up and the output voltage is driven

to the specified value as determined by the volatile

DAC register and configuration bits.

A write command forcing the PD1:PD0 bits to ‘00’, will

cause the device to exit the power-down mode.

5.7

DAC Registers, Configuration

Bits, and Status Bits

The MCP48FEBXX devices have both volatile and

nonvolatile (EEPROM) memory. Table 4-2 shows the

volatile and non-volatile memory and their interaction

due to a POR event.

There are five configuration bits in both the volatile and

nonvolatile memory, the DAC registers in both the

volatile and nonvolatile memory, and two volatile status

bits. The DAC registers (volatile and nonvolatile) will be

either 12 bits (MCP48FEB2X), 10 bits (MCP48FEB1X),

or 8 bits (MCP48FEB0X) wide.

When the device is first powered-up, it automatically

uploads the EEPROM memory values to the volatile

memory. The volatile memory determines the analog

output (VOUT) pin voltage. After the device is

powered-up, the user can update the device memory.

The SPI interface is how this memory is read and

written. Refer to Section 6.0 “SPI Serial Interface

Module”

and Section 7.0 “SPI Commands” for more

details on reading and writing the device’s memory.

When the nonvolatile memory is written, the device

starts writing the EEPROM cell at the rising edge of the

CS pin.

bits, Table 4-1 and Table 4-3 show the operation of the

device configuration bits, and Table 4-2 shows the

factory default value of a POR/BOR event for the

device configuration bits.

There are two status bits. These are only in volatile

memory and give indication on the status of the device.

The POR bit indicates if the device VDD is above or

below the POR trip point. During normal operation, this

bit should be ‘1’. The EEWA bit indicates if an

EEPROM write cycle is in progress. While the EEWA

bit is low (during the EEPROM writing), all commands

are ignored, except for the Read command.

Note:

Since the op amp and resistor ladder were

powered-off (0V), the op amp’s input

voltage (VW) can be considered 0V. There

is a delay (TPDD) between the PD1:PD0

bits updating to ‘00’ and the op amp

driving the VOUT output. The op amp’s

settling time (from 0V) needs to be taken

into account to ensure the VOUT voltage

reflects the selected value.

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